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[Qemu-devel] [PULL 06/29] target/arm: Pass in pc to thumb_insn_is_16bit
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 06/29] target/arm: Pass in pc to thumb_insn_is_16bit |
Date: |
Fri, 16 Aug 2019 14:16:56 +0100 |
From: Richard Henderson <address@hidden>
This function is used in two different contexts, and it will be
clearer if the function is given the address to which it applies.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index b32508cd2f9..de941e6b3dc 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9246,11 +9246,11 @@ static void disas_arm_insn(DisasContext *s, unsigned
int insn)
}
}
-static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
+static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn)
{
- /* Return true if this is a 16 bit instruction. We must be precise
- * about this (matching the decode). We assume that s->pc still
- * points to the first 16 bits of the insn.
+ /*
+ * Return true if this is a 16 bit instruction. We must be precise
+ * about this (matching the decode).
*/
if ((insn >> 11) < 0x1d) {
/* Definitely a 16-bit instruction */
@@ -9270,7 +9270,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t
insn)
return false;
}
- if ((insn >> 11) == 0x1e && s->pc - s->page_start < TARGET_PAGE_SIZE - 3) {
+ if ((insn >> 11) == 0x1e && pc - s->page_start < TARGET_PAGE_SIZE - 3) {
/* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix
* is not on the next page; we merge this into a 32-bit
* insn.
@@ -11809,7 +11809,7 @@ static bool insn_crosses_page(CPUARMState *env,
DisasContext *s)
*/
uint16_t insn = arm_lduw_code(env, s->pc, s->sctlr_b);
- return !thumb_insn_is_16bit(s, insn);
+ return !thumb_insn_is_16bit(s, s->pc, insn);
}
static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
@@ -12108,7 +12108,7 @@ static void thumb_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cpu)
}
insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);
- is_16bit = thumb_insn_is_16bit(dc, insn);
+ is_16bit = thumb_insn_is_16bit(dc, dc->pc, insn);
dc->pc += 2;
if (!is_16bit) {
uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b);
--
2.20.1
- [Qemu-devel] [PULL 00/29] target-arm queue, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 03/29] Set ENET_BD_BDU in I.MX FEC controller, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 01/29] target/arm: generate a custom MIDR for -cpu max, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 04/29] target/arm: Factor out 'generate singlestep exception' function, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 06/29] target/arm: Pass in pc to thumb_insn_is_16bit,
Peter Maydell <=
- [Qemu-devel] [PULL 07/29] target/arm: Introduce pc_curr, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 02/29] hw/misc/zynq_slcr: use standard register definition, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 09/29] target/arm: Introduce add_reg_for_lit, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 08/29] target/arm: Introduce read_pc, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 16/29] target/arm: Remove helper_double_saturate, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 14/29] target/arm: Remove offset argument to gen_exception_bkpt_insn, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 13/29] target/arm: Replace offset with pc in gen_exception_internal_insn, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 19/29] target/arm/helper: zcr: Add build bug next to value range assumption, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 17/29] target/arm/cpu64: Ensure kvm really supports aarch64=off, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 05/29] target/arm: Fix routing of singlestep exceptions, Peter Maydell, 2019/08/16