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[Qemu-devel] [PATCH 12/26] target/mips: Clean up handling of CP0 registe
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH 12/26] target/mips: Clean up handling of CP0 register 15 |
Date: |
Thu, 22 Aug 2019 13:35:36 +0200 |
From: Aleksandar Markovic <address@hidden>
Clean up handling of CP0 register 15.
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 20 ++++++++++----------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index d61b8c0..3a8c560 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -363,6 +363,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG15__EBASE 1
#define CP0_REG15__CDMMBASE 2
#define CP0_REG15__CMGCRBASE 3
+#define CP0_REG15__BEVVA 4
/* CP0 Register 16 */
#define CP0_REG16__CONFIG 0
#define CP0_REG16__CONFIG1 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 642c108..97a274a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7270,17 +7270,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EBase";
break;
- case 3:
+ case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@@ -8007,11 +8007,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
/* ignored */
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
@@ -8756,16 +8756,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
register_name = "EBase";
break;
- case 3:
+ case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@@ -9482,11 +9482,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
/* ignored */
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
--
2.7.4
- [Qemu-devel] [PATCH 09/26] target/mips: Clean up handling of CP0 register 10, (continued)
- [Qemu-devel] [PATCH 09/26] target/mips: Clean up handling of CP0 register 10, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 01/26] target/mips: Clean up handling of CP0 register 0, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 07/26] target/mips: Clean up handling of CP0 register 8, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 04/26] target/mips: Clean up handling of CP0 register 5, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 02/26] target/mips: Clean up handling of CP0 register 1, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 06/26] target/mips: Clean up handling of CP0 register 7, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 08/26] target/mips: Clean up handling of CP0 register 9, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 16/26] target/mips: Clean up handling of CP0 register 19, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 14/26] target/mips: Clean up handling of CP0 register 17, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 13/26] target/mips: Clean up handling of CP0 register 16, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 12/26] target/mips: Clean up handling of CP0 register 15,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH 03/26] target/mips: Clean up handling of CP0 register 2, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 15/26] target/mips: Clean up handling of CP0 register 18, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 11/26] target/mips: Clean up handling of CP0 register 12, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 05/26] target/mips: Clean up handling of CP0 register 6, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 19/26] target/mips: Clean up handling of CP0 register 24, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 22/26] target/mips: Clean up handling of CP0 register 27, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 25/26] target/mips: Clean up handling of CP0 register 30, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 17/26] target/mips: Clean up handling of CP0 register 20, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 21/26] target/mips: Clean up handling of CP0 register 26, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 18/26] target/mips: Clean up handling of CP0 register 23, Aleksandar Markovic, 2019/08/22