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[Qemu-devel] [PATCH v1 07/28] target/riscv: Dump Hypervisor registers if
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v1 07/28] target/riscv: Dump Hypervisor registers if enabled |
Date: |
Fri, 23 Aug 2019 16:38:07 -0700 |
Dump the Hypervisor registers and the current Hypervisor state.
While we are editing this code let's also dump stvec and scause.
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Atish Patra <address@hidden>
---
target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f13e298a36..be8f643fc2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -220,18 +220,52 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
int flags)
CPURISCVState *env = &cpu->env;
int i;
+#if !defined(CONFIG_USER_ONLY)
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env));
+ }
+#endif
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
#ifndef CONFIG_USER_ONLY
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "bstatus ", env->vsstatus);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ",
(target_ulong)atomic_read(&env->mip));
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsip ",
+ (target_ulong)atomic_read(&env->vsip));
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsie ", env->vsie);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
+ }
#endif
for (i = 0; i < 32; i++) {
--
2.22.0
- [Qemu-devel] [PATCH v1 00/28] Add RISC-V Hypervisor Extension v0.4, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 02/28] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 04/28] target/riscv: Fix CSR perm checking for HS mode, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 03/28] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 06/28] target/riscv: Print priv and virt in disas log, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 08/28] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 07/28] target/riscv: Dump Hypervisor registers if enabled,
Alistair Francis <=
- [Qemu-devel] [PATCH v1 09/28] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 12/28] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 11/28] target/riscv: Add background register swapping function, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 13/28] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 14/28] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 16/28] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 15/28] riscv: plic: Always set sip.SEIP bit for HS, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 17/28] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 19/28] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2019/08/23