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[Qemu-devel] [PATCH v1 15/28] riscv: plic: Always set sip.SEIP bit for H
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v1 15/28] riscv: plic: Always set sip.SEIP bit for HS |
Date: |
Fri, 23 Aug 2019 16:38:29 -0700 |
When the PLIC generates an interrupt ensure we always set it for the SIP
CSR that corresponds to the HS (V=0) register.
Signed-off-by: Alistair Francis <address@hidden>
---
hw/riscv/sifive_plic.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index 98e4304b66..8309e96f64 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -150,7 +150,17 @@ static void sifive_plic_update(SiFivePLICState *plic)
riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP,
BOOL_TO_MASK(level));
break;
case PLICMode_S:
- riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP,
BOOL_TO_MASK(level));
+ if (riscv_cpu_virt_enabled(env)) {
+ if (level) {
+ atomic_or(&env->mip_novirt, MIP_SEIP);
+ g_assert(riscv_cpu_virt_enabled(env));
+ } else {
+ atomic_and(&env->mip_novirt, ~MIP_SEIP);
+ g_assert(riscv_cpu_virt_enabled(env));
+ }
+ } else {
+ riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP,
BOOL_TO_MASK(level));
+ }
break;
default:
break;
--
2.22.0
- [Qemu-devel] [PATCH v1 06/28] target/riscv: Print priv and virt in disas log, (continued)
- [Qemu-devel] [PATCH v1 06/28] target/riscv: Print priv and virt in disas log, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 08/28] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 07/28] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 09/28] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 12/28] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 11/28] target/riscv: Add background register swapping function, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 13/28] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 14/28] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 16/28] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 15/28] riscv: plic: Always set sip.SEIP bit for HS,
Alistair Francis <=
- [Qemu-devel] [PATCH v1 17/28] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 19/28] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 18/28] target/riscv: Add hfence instructions, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 20/28] target/riscv: Mark both sstatus and vsstatus as dirty, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 21/28] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 22/28] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 23/28] target/riscv: Allow specifying number of MMU stages, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 24/28] target/riscv: Implement second stage MMU, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 25/28] target/riscv: Call the second stage MMU in virtualisation mode, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 26/28] target/riscv: Add support for the 32-bit MSTATUSH CSR, Alistair Francis, 2019/08/23