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Re: [Qemu-devel] [PATCH 04/13] target/openrisc: Make VR and PPC read-onl
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From: |
Stafford Horne |
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Subject: |
Re: [Qemu-devel] [PATCH 04/13] target/openrisc: Make VR and PPC read-only |
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Date: |
Tue, 27 Aug 2019 13:33:23 +0900 |
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User-agent: |
Mutt/1.11.4 (2019-03-13) |
On Mon, Aug 26, 2019 at 05:07:36PM -0700, Richard Henderson wrote:
> These SPRs are read-only. The writes can simply be ignored,
> as we already do for other read-only (or missing) registers.
> There is no reason to mask the value in env->vr.
>
> Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Stafford Horne <address@hidden>
- [Qemu-devel] [PATCH 00/13] target/openrisc updates, Richard Henderson, 2019/08/26
- [Qemu-devel] [PATCH 01/13] target/openrisc: Add DisasContext parameter to check_r0_write, Richard Henderson, 2019/08/26
- [Qemu-devel] [PATCH 03/13] target/openrisc: Cache R0 in DisasContext, Richard Henderson, 2019/08/26
- [Qemu-devel] [PATCH 04/13] target/openrisc: Make VR and PPC read-only, Richard Henderson, 2019/08/26
- Re: [Qemu-devel] [PATCH 04/13] target/openrisc: Make VR and PPC read-only,
Stafford Horne <=
- [Qemu-devel] [PATCH 05/13] target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init, Richard Henderson, 2019/08/26
- [Qemu-devel] [PATCH 02/13] target/openrisc: Replace cpu register array with a function, Richard Henderson, 2019/08/26
- [Qemu-devel] [PATCH 06/13] target/openrisc: Add VR2 and AVR special processor registers, Richard Henderson, 2019/08/26
- [Qemu-devel] [PATCH 07/13] target/openrisc: Fix lf.ftoi.s, Richard Henderson, 2019/08/26
- [Qemu-devel] [PATCH 08/13] target/openrisc: Check CPUCFG_OF32S for float insns, Richard Henderson, 2019/08/26