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Re: [Qemu-devel] [Qemu-riscv] [PATCH v1 05/28] target/riscv: Add the Hyp
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From: |
Chih-Min Chao |
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Subject: |
Re: [Qemu-devel] [Qemu-riscv] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState |
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Date: |
Tue, 27 Aug 2019 23:50:52 +0800 |
On Sat, Aug 24, 2019 at 7:45 AM Alistair Francis <address@hidden>
wrote:
> As the MIP CSR is 32-bits to allow atomic_read on 32-bit hosts the vsip
> is 32-bit as well.
>
> Signed-off-by: Alistair Francis <address@hidden>
> ---
> target/riscv/cpu.h | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 3a95c41428..4c342e7a79 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -154,6 +154,23 @@ struct CPURISCVState {
> target_ulong mcause;
> target_ulong mtval; /* since: priv-1.10.0 */
>
> + /* Hypervisor CSRs */
> + target_ulong hstatus;
> + target_ulong hedeleg;
> + target_ulong hideleg;
> + target_ulong hgatp;
> +
> + /* Virtual CSRs */
> + target_ulong vsstatus;
> + uint32_t vsip;
> + target_ulong vsie;
> + target_ulong vstvec;
> + target_ulong vsscratch;
> + target_ulong vsepc;
> + target_ulong vscause;
> + target_ulong vstval;
> + target_ulong vsatp;
> +
> target_ulong scounteren;
> target_ulong mcounteren;
>
> --
> 2.22.0
>
>
Reviewed-by: Chih-Min Chao <address@hidden>
- [Qemu-devel] [PATCH v1 00/28] Add RISC-V Hypervisor Extension v0.4, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 02/28] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 04/28] target/riscv: Fix CSR perm checking for HS mode, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 03/28] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/08/23
- Re: [Qemu-devel] [Qemu-riscv] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState,
Chih-Min Chao <=
- [Qemu-devel] [PATCH v1 06/28] target/riscv: Print priv and virt in disas log, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 08/28] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 07/28] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 09/28] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 12/28] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 11/28] target/riscv: Add background register swapping function, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 13/28] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 14/28] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 16/28] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/08/23