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[Qemu-devel] [PULL 05/31] target/mips: Clean up handling of CP0 register
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 05/31] target/mips: Clean up handling of CP0 register 4 |
Date: |
Thu, 29 Aug 2019 12:24:47 +0200 |
From: Aleksandar Markovic <address@hidden>
Clean up handling of CP0 register 4.
Reviewed-by: Aleksandar Rikalo <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Message-Id: <address@hidden>
---
target/mips/cpu.h | 2 ++
target/mips/translate.c | 36 ++++++++++++++++++++----------------
2 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index d5b7103..496872e 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -305,7 +305,9 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG03__TCOPT 7
/* CP0 Register 04 */
#define CP0_REG04__CONTEXT 0
+#define CP0_REG04__CONTEXTCONFIG 1
#define CP0_REG04__USERLOCAL 2
+#define CP0_REG04__XCONTEXTCONFIG 3
#define CP0_REG04__DBGCONTEXTID 4
#define CP0_REG00__MMID 5
/* CP0 Register 05 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 059f53e..9df59f1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6975,16 +6975,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
- case 0:
+ case CP0_REG04__CONTEXT:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
tcg_gen_ext32s_tl(arg, arg);
register_name = "Context";
break;
- case 1:
- /* gen_helper_mfc0_contextconfig(arg); - SmartMIPS ASE */
+ case CP0_REG04__CONTEXTCONFIG:
+ /* SmartMIPS ASE */
+ /* gen_helper_mfc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
@@ -7710,15 +7711,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
- case 0:
+ case CP0_REG04__CONTEXT:
gen_helper_mtc0_context(cpu_env, arg);
register_name = "Context";
break;
- case 1:
-// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
+ case CP0_REG04__CONTEXTCONFIG:
+ /* SmartMIPS ASE */
+ /* gen_helper_mtc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
@@ -8455,15 +8457,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
- case 0:
+ case CP0_REG04__CONTEXT:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
register_name = "Context";
break;
- case 1:
-// gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
+ case CP0_REG04__CONTEXTCONFIG:
+ /* SmartMIPS ASE */
+ /* gen_helper_dmfc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
@@ -9168,15 +9171,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
- case 0:
+ case CP0_REG04__CONTEXT:
gen_helper_mtc0_context(cpu_env, arg);
register_name = "Context";
break;
- case 1:
-// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
+ case CP0_REG04__CONTEXTCONFIG:
+ /* SmartMIPS ASE */
+ /* gen_helper_dmtc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
--
2.7.4
- [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 01/31] target/mips: Clean up handling of CP0 register 0, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 02/31] target/mips: Clean up handling of CP0 register 1, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 05/31] target/mips: Clean up handling of CP0 register 4,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 08/31] target/mips: Clean up handling of CP0 register 7, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 03/31] target/mips: Clean up handling of CP0 register 2, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 10/31] target/mips: Clean up handling of CP0 register 9, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 15/31] target/mips: Clean up handling of CP0 register 14, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 06/31] target/mips: Clean up handling of CP0 register 5, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 07/31] target/mips: Clean up handling of CP0 register 6, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 24/31] target/mips: Clean up handling of CP0 register 25, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 12/31] target/mips: Clean up handling of CP0 register 11, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 09/31] target/mips: Clean up handling of CP0 register 8, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 11/31] target/mips: Clean up handling of CP0 register 10, Aleksandar Markovic, 2019/08/29