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[Qemu-devel] [PULL 06/31] target/mips: Clean up handling of CP0 register
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 06/31] target/mips: Clean up handling of CP0 register 5 |
Date: |
Thu, 29 Aug 2019 12:24:48 +0200 |
From: Aleksandar Markovic <address@hidden>
Clean up handling of CP0 register 5.
Reviewed-by: Aleksandar Rikalo <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Message-Id: <address@hidden>
---
target/mips/cpu.h | 6 +++++
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 38 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 496872e..ed1a974 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -313,6 +313,12 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 05 */
#define CP0_REG05__PAGEMASK 0
#define CP0_REG05__PAGEGRAIN 1
+#define CP0_REG05__SEGCTL0 2
+#define CP0_REG05__SEGCTL1 3
+#define CP0_REG05__SEGCTL2 4
+#define CP0_REG05__PWBASE 5
+#define CP0_REG05__PWFIELD 6
+#define CP0_REG05__PWSIZE 7
/* CP0 Register 06 */
#define CP0_REG06__WIRED 0
/* CP0 Register 07 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9df59f1..19f86f2 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6998,44 +6998,44 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
- case 0:
+ case CP0_REG05__PAGEMASK:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
register_name = "PageMask";
break;
- case 1:
+ case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain";
break;
- case 2:
+ case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl0";
break;
- case 3:
+ case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl1";
break;
- case 4:
+ case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl2";
break;
- case 5:
+ case CP0_REG05__PWBASE:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
- case 6:
+ case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField));
register_name = "PWField";
break;
- case 7:
+ case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize));
register_name = "PWSize";
@@ -7732,42 +7732,42 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
- case 0:
+ case CP0_REG05__PAGEMASK:
gen_helper_mtc0_pagemask(cpu_env, arg);
register_name = "PageMask";
break;
- case 1:
+ case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain";
ctx->base.is_jmp = DISAS_STOP;
break;
- case 2:
+ case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl0(cpu_env, arg);
register_name = "SegCtl0";
break;
- case 3:
+ case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl1(cpu_env, arg);
register_name = "SegCtl1";
break;
- case 4:
+ case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl2(cpu_env, arg);
register_name = "SegCtl2";
break;
- case 5:
+ case CP0_REG05__PWBASE:
check_pw(ctx);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
- case 6:
+ case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_helper_mtc0_pwfield(cpu_env, arg);
register_name = "PWField";
break;
- case 7:
+ case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_helper_mtc0_pwsize(cpu_env, arg);
register_name = "PWSize";
@@ -8478,41 +8478,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
- case 0:
+ case CP0_REG05__PAGEMASK:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
register_name = "PageMask";
break;
- case 1:
+ case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain";
break;
- case 2:
+ case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
register_name = "SegCtl0";
break;
- case 3:
+ case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
register_name = "SegCtl1";
break;
- case 4:
+ case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
register_name = "SegCtl2";
break;
- case 5:
+ case CP0_REG05__PWBASE:
check_pw(ctx);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
- case 6:
+ case CP0_REG05__PWFIELD:
check_pw(ctx);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField));
register_name = "PWField";
break;
- case 7:
+ case CP0_REG05__PWSIZE:
check_pw(ctx);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize));
register_name = "PWSize";
@@ -9192,41 +9192,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
- case 0:
+ case CP0_REG05__PAGEMASK:
gen_helper_mtc0_pagemask(cpu_env, arg);
register_name = "PageMask";
break;
- case 1:
+ case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain";
break;
- case 2:
+ case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl0(cpu_env, arg);
register_name = "SegCtl0";
break;
- case 3:
+ case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl1(cpu_env, arg);
register_name = "SegCtl1";
break;
- case 4:
+ case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl2(cpu_env, arg);
register_name = "SegCtl2";
break;
- case 5:
+ case CP0_REG05__PWBASE:
check_pw(ctx);
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
- case 6:
+ case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_helper_mtc0_pwfield(cpu_env, arg);
register_name = "PWField";
break;
- case 7:
+ case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_helper_mtc0_pwsize(cpu_env, arg);
register_name = "PWSize";
--
2.7.4
- [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 01/31] target/mips: Clean up handling of CP0 register 0, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 02/31] target/mips: Clean up handling of CP0 register 1, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 05/31] target/mips: Clean up handling of CP0 register 4, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 08/31] target/mips: Clean up handling of CP0 register 7, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 03/31] target/mips: Clean up handling of CP0 register 2, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 10/31] target/mips: Clean up handling of CP0 register 9, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 15/31] target/mips: Clean up handling of CP0 register 14, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 06/31] target/mips: Clean up handling of CP0 register 5,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 07/31] target/mips: Clean up handling of CP0 register 6, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 24/31] target/mips: Clean up handling of CP0 register 25, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 12/31] target/mips: Clean up handling of CP0 register 11, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 09/31] target/mips: Clean up handling of CP0 register 8, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 11/31] target/mips: Clean up handling of CP0 register 10, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 13/31] target/mips: Clean up handling of CP0 register 12, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 04/31] target/mips: Clean up handling of CP0 register 3, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 16/31] target/mips: Clean up handling of CP0 register 15, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 26/31] target/mips: Clean up handling of CP0 register 27, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 22/31] target/mips: Clean up handling of CP0 register 23, Aleksandar Markovic, 2019/08/29