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[PATCH v2 05/27] target/riscv: Fix CSR perm checking for HS mode
From: |
Alistair Francis |
Subject: |
[PATCH v2 05/27] target/riscv: Fix CSR perm checking for HS mode |
Date: |
Fri, 25 Oct 2019 16:23:25 -0700 |
Update the CSR permission checking to work correctly when we are in
HS-mode.
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/csr.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index da02f9f0b1..08956aa557 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -799,12 +799,22 @@ int riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
/* check privileges and return -1 if check fails */
#if !defined(CONFIG_USER_ONLY)
- int csr_priv = get_field(csrno, 0x300);
+ int effective_priv = env->priv;
int read_only = get_field(csrno, 0xC00) == 3;
- if ((!env->debugger) && (env->priv < csr_priv)) {
- return -1;
+
+ if (riscv_has_ext(env, RVH) &&
+ env->priv == PRV_S &&
+ !riscv_cpu_virt_enabled(env)) {
+ /*
+ * We are in S mode without virtualisation, therefore we are in HS
Mode.
+ * Add 1 to the effective privledge level to allow us to access the
+ * Hypervisor CSRs.
+ */
+ effective_priv++;
}
- if (write_mask && read_only) {
+
+ if ((write_mask && read_only) ||
+ (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
return -1;
}
#endif
--
2.23.0
- [PATCH v2 00/27] Add RISC-V Hypervisor Extension v0.4, Alistair Francis, 2019/10/25
- [PATCH v2 01/27] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/10/25
- [PATCH v2 02/27] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/10/25
- [PATCH v2 04/27] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/10/25
- [PATCH v2 05/27] target/riscv: Fix CSR perm checking for HS mode,
Alistair Francis <=
- [PATCH v2 06/27] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/10/25
- [PATCH v2 03/27] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/10/25
- [PATCH v2 08/27] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/10/25
- [PATCH v2 07/27] target/riscv: Print priv and virt in disas log, Alistair Francis, 2019/10/25
- [PATCH v2 10/27] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/10/25
- [PATCH v2 11/27] target/riscv: Convert mie and mstatus to pointers, Alistair Francis, 2019/10/25
- [PATCH v2 17/27] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/10/25
- [PATCH v2 09/27] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/10/25
- [PATCH v2 18/27] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/10/25
- [PATCH v2 19/27] target/riscv: Add hfence instructions, Alistair Francis, 2019/10/25