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[PATCH v2 07/27] target/riscv: Print priv and virt in disas log
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From: |
Alistair Francis |
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Subject: |
[PATCH v2 07/27] target/riscv: Print priv and virt in disas log |
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Date: |
Fri, 25 Oct 2019 16:23:32 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
---
target/riscv/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index adeddb85f6..8ac72c6470 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -810,7 +810,15 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cpu)
static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
{
+#ifndef CONFIG_USER_ONLY
+ RISCVCPU *rvcpu = RISCV_CPU(cpu);
+ CPURISCVState *env = &rvcpu->env;
+#endif
+
qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
+#ifndef CONFIG_USER_ONLY
+ qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv,
env->virt);
+#endif
log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
}
--
2.23.0
- [PATCH v2 00/27] Add RISC-V Hypervisor Extension v0.4, Alistair Francis, 2019/10/25
- [PATCH v2 01/27] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/10/25
- [PATCH v2 02/27] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/10/25
- [PATCH v2 04/27] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/10/25
- [PATCH v2 05/27] target/riscv: Fix CSR perm checking for HS mode, Alistair Francis, 2019/10/25
- [PATCH v2 06/27] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/10/25
- [PATCH v2 03/27] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/10/25
- [PATCH v2 08/27] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/10/25
- [PATCH v2 07/27] target/riscv: Print priv and virt in disas log,
Alistair Francis <=
- [PATCH v2 10/27] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/10/25
- [PATCH v2 11/27] target/riscv: Convert mie and mstatus to pointers, Alistair Francis, 2019/10/25
- [PATCH v2 17/27] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/10/25
- [PATCH v2 09/27] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/10/25
- [PATCH v2 18/27] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/10/25
- [PATCH v2 19/27] target/riscv: Add hfence instructions, Alistair Francis, 2019/10/25
- [PATCH v2 20/27] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2019/10/25
- [PATCH v2 21/27] target/riscv: Mark both sstatus and vsstatus as dirty, Alistair Francis, 2019/10/25
- [PATCH v2 13/27] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2019/10/25
- [PATCH v2 15/27] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/10/25