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Re: [PATCH v6 06/20] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() help
From: |
David Gibson |
Subject: |
Re: [PATCH v6 06/20] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper |
Date: |
Wed, 27 Nov 2019 16:01:23 +1100 |
User-agent: |
Mutt/1.12.1 (2019-06-15) |
On Mon, Nov 25, 2019 at 07:58:06AM +0100, Cédric Le Goater wrote:
> and use this helper to exclude CPUs which are not enabled in the XIVE
> controller.
>
> Signed-off-by: Cédric Le Goater <address@hidden>
Applied 5..6 to ppc-for-5.0.
> ---
> include/hw/ppc/pnv.h | 5 +++++
> hw/intc/pnv_xive.c | 19 +++++++++++++++++++
> 2 files changed, 24 insertions(+)
>
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index 03cb429f2131..12b0169a4010 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -99,6 +99,11 @@ typedef struct Pnv9Chip {
> PnvQuad *quads;
> } Pnv9Chip;
>
> +/*
> + * A SMT8 fused core is a pair of SMT4 cores.
> + */
> +#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
> +
> typedef struct PnvChipClass {
> /*< private >*/
> SysBusDeviceClass parent_class;
> diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
> index 9798bd9e729f..ec8349ee4a1f 100644
> --- a/hw/intc/pnv_xive.c
> +++ b/hw/intc/pnv_xive.c
> @@ -372,6 +372,21 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t
> blk, uint32_t idx,
> return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas);
> }
>
> +/*
> + * One bit per thread id. The first register PC_THREAD_EN_REG0 covers
> + * the first cores 0-15 (normal) of the chip or 0-7 (fused). The
> + * second register covers cores 16-23 (normal) or 8-11 (fused).
> + */
> +static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu)
> +{
> + int pir = ppc_cpu_pir(cpu);
> + uint32_t fc = PNV9_PIR2FUSEDCORE(pir);
> + uint64_t reg = fc < 8 ? PC_THREAD_EN_REG0 : PC_THREAD_EN_REG1;
> + uint32_t bit = pir & 0x3f;
> +
> + return xive->regs[reg >> 3] & PPC_BIT(bit);
> +}
> +
> static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
> uint8_t nvt_blk, uint32_t nvt_idx,
> bool cam_ignore, uint8_t priority,
> @@ -391,6 +406,10 @@ static int pnv_xive_match_nvt(XivePresenter *xptr,
> uint8_t format,
> XiveTCTX *tctx;
> int ring;
>
> + if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
> + continue;
> + }
> +
> tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
>
> /*
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests, Cédric Le Goater, 2019/11/25
- [PATCH v6 02/20] ppc/xive: Implement the XivePresenter interface, Cédric Le Goater, 2019/11/25
- [PATCH v6 01/20] ppc/xive: Introduce a XivePresenter interface, Cédric Le Goater, 2019/11/25
- [PATCH v6 03/20] ppc/pnv: Instantiate cores separately, Cédric Le Goater, 2019/11/25
- [PATCH v6 04/20] ppc/pnv: Loop on the threads of the chip to find a matching NVT, Cédric Le Goater, 2019/11/25
- [PATCH v6 05/20] ppc: Introduce a ppc_cpu_pir() helper, Cédric Le Goater, 2019/11/25
- [PATCH v6 06/20] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper, Cédric Le Goater, 2019/11/25
- Re: [PATCH v6 06/20] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper,
David Gibson <=
- [PATCH v6 07/20] ppc/pnv: Fix TIMA indirect access, Cédric Le Goater, 2019/11/25
- [PATCH v6 08/20] ppc/xive: Introduce a XiveFabric interface, Cédric Le Goater, 2019/11/25
- [PATCH v6 09/20] ppc/pnv: Implement the XiveFabric interface, Cédric Le Goater, 2019/11/25
- [PATCH v6 10/20] ppc/spapr: Implement the XiveFabric interface, Cédric Le Goater, 2019/11/25
- [PATCH v6 11/20] ppc/xive: Use the XiveFabric and XivePresenter interfaces, Cédric Le Goater, 2019/11/25
- [PATCH v6 12/20] ppc/xive: Extend the TIMA operation with a XivePresenter parameter, Cédric Le Goater, 2019/11/25
- [PATCH v6 13/20] ppc/pnv: Clarify how the TIMA is accessed on a multichip system, Cédric Le Goater, 2019/11/25