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From: | Tao Xu |
Subject: | Re: [PATCH v18 3/8] numa: Extend CLI to provide memory side cache information |
Date: | Thu, 28 Nov 2019 10:46:07 +0800 |
User-agent: | Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 |
On 11/27/2019 5:56 PM, Markus Armbruster wrote:
Tao Xu <address@hidden> writes:From: Liu Jingqi <address@hidden> Add -numa hmat-cache option to provide Memory Side Cache Information. These memory attributes help to build Memory Side Cache Information Structure(s) in ACPI Heterogeneous Memory Attribute Table (HMAT).Please mention this requires -machine hmat=on.
OK I will add these for 3 related patches.
Reviewed-by: Igor Mammedov <address@hidden> Reviewed-by: Daniel Black <address@hidden> Signed-off-by: Liu Jingqi <address@hidden> Signed-off-by: Tao Xu <address@hidden>[...]diff --git a/qapi/machine.json b/qapi/machine.json index c741649d7b..3d0ba226a9 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -428,10 +428,12 @@ # # @hmat-lb: memory latency and bandwidth information (Since: 5.0) # +# @hmat-cache: memory side cache information (Since: 5.0) +# # Since: 2.1 ## { 'enum': 'NumaOptionsType', - 'data': [ 'node', 'dist', 'cpu', 'hmat-lb' ] } + 'data': [ 'node', 'dist', 'cpu', 'hmat-lb', 'hmat-cache' ] }### @NumaOptions: @@ -447,7 +449,8 @@ 'node': 'NumaNodeOptions', 'dist': 'NumaDistOptions', 'cpu': 'NumaCpuOptions', - 'hmat-lb': 'NumaHmatLBOptions' }} + 'hmat-lb': 'NumaHmatLBOptions', + 'hmat-cache': 'NumaHmatCacheOptions' }}### @NumaNodeOptions: @@ -647,6 +650,77 @@ '*latency': 'uint64', '*bandwidth': 'size' }}+##+# @HmatCacheAssociativity: +# +# Cache associativity in the Memory Side Cache +# Information Structure of HMAT +# +# For more information of @HmatCacheAssociativity see +# the chapter 5.2.27.5: Table 5-147 of ACPI 6.3 spec.# Cache associativity in the Memory Side Cache Information Structure # of HMAT # # For more information of @HmatCacheAssociativity, see chapter # 5.2.27.5: Table 5-147 of ACPI 6.3 spec.+# +# @none: NoneWhat does cache associativity @none mean? A none-associative cache? I guess it makes sense to people familiar with the ACPI spec...
This means this proximity domain has no memory cache, thus none for Cache associativity, I will add more description about this.
+# +# @direct: Direct Mapped +# +# @complex: Complex Cache Indexing (implementation specific) +# +# Since: 5.0 +## +{ 'enum': 'HmatCacheAssociativity', + 'data': [ 'none', 'direct', 'complex' ] } + +## +# @HmatCacheWritePolicy: +# +# Cache write policy in the Memory Side Cache +# Information Structure of HMAT +# +# For more information of @HmatCacheWritePolicy see +# the chapter 5.2.27.5: Table 5-147: Field "Cache Attributes" of ACPI 6.3 spec.Break lines around column 70, please.+# +# @none: NoneWhat does cache write policy @none mean?
This means this proximity domain has no memory cache, thus none for cache write policy.
+# +# @write-back: Write Back (WB) +# +# @write-through: Write Through (WT) +# +# Since: 5.0 +## +{ 'enum': 'HmatCacheWritePolicy', + 'data': [ 'none', 'write-back', 'write-through' ] } + +## +# @NumaHmatCacheOptions: +# +# Set the memory side cache information for a given memory domain. +# +# For more information of @NumaHmatCacheOptions see +# the chapter 5.2.27.5: Table 5-147: Field "Cache Attributes" of ACPI 6.3 spec. +# +# @node-id: the memory proximity domain to which the memory belongs. +# +# @size: the size of memory side cache in bytes. +# +# @level: the cache level described in this structure. +# +# @assoc: the cache associativity, none/direct-mapped/complex(complex cache indexing). +# +# @policy: the write policy, none/write-back/write-through. +# +# @line: the cache Line size in bytes. +# +# Since: 5.0 +## +{ 'struct': 'NumaHmatCacheOptions', + 'data': { + 'node-id': 'uint32',Ignorant question: you use 'uint16' for other "proximity domains". Is 'uint32' intentional here?
Yes, because ACPI 6.3 spec define the domain as 4 byte(32 bit), and for HmatCacheOptions we directly use this QAPI struct when building HMAT. But for other "proximity domains" we use local variable (such as "uint32_t initiator")
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