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Re: [PATCH v37 05/17] target/avr: Add instruction translation - Arithmet
From: |
Aleksandar Markovic |
Subject: |
Re: [PATCH v37 05/17] target/avr: Add instruction translation - Arithmetic and Logic Instructions |
Date: |
Sat, 30 Nov 2019 11:33:26 +0100 |
On Wednesday, November 27, 2019, Michael Rolnik <address@hidden> wrote:
+
+
+/*
+ * Performs the logical AND between the contents of register Rd and register
+ * Rr and places the result in the destination register Rd.
+ */
+static bool trans_AND(DisasContext *ctx, arg_AND *a)
+{
+ TCGv Rd = cpu_r[a->rd];
+ TCGv Rr = cpu_r[a->rr];
+ TCGv R = tcg_temp_new_i32();
+
+ /* op */
+ tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */
+
+ /* Vf */
+ tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */
+
+ /* Zf */
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */
+
+ gen_ZNSf(R);
+
+ /* R */
+ tcg_gen_mov_tl(Rd, R);
+
+ tcg_temp_free_i32(R);
+
+ return true;
+}
+
+
According to specs:
... the chips in question have cores with 16 GPRs (that correspond to GPRs R16-R31 of more common AVR cores with 32 GPRs).
How do you handle such cores?
I don't see here anything preventing usage of all 32 GPRs, resulting, of course, in an inaccurate emulation.
Thanks,
Aleksandar
- [PATCH v37 00/17] QEMU AVR 8 bit cores, Michael Rolnik, 2019/11/27
- [PATCH v37 03/17] target/avr: Add instruction decoding, Michael Rolnik, 2019/11/27
- [PATCH v37 02/17] target/avr: Add instruction helpers, Michael Rolnik, 2019/11/27
- [PATCH v37 01/17] target/avr: Add outward facing interfaces and core CPU logic, Michael Rolnik, 2019/11/27
- [PATCH v37 04/17] target/avr: Add instruction translation - Registers definition, Michael Rolnik, 2019/11/27
- [PATCH v37 05/17] target/avr: Add instruction translation - Arithmetic and Logic Instructions, Michael Rolnik, 2019/11/27
- Re: [PATCH v37 05/17] target/avr: Add instruction translation - Arithmetic and Logic Instructions,
Aleksandar Markovic <=
[PATCH v37 06/17] target/avr: Add instruction translation - Branch Instructions, Michael Rolnik, 2019/11/27
[PATCH v37 09/17] target/avr: Add instruction translation - CPU main translation function, Michael Rolnik, 2019/11/27
[PATCH v37 07/17] target/avr: Add instruction translation - Bit and Bit-test Instructions, Michael Rolnik, 2019/11/27
[PATCH v37 08/17] target/avr: Add instruction translation - MCU Control Instructions, Michael Rolnik, 2019/11/27
[PATCH v37 10/17] target/avr: Add instruction disassembly function, Michael Rolnik, 2019/11/27
[PATCH v37 13/17] target/avr: Register AVR support with the rest of QEMU, Michael Rolnik, 2019/11/27