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[PATCH v4 23/40] target/arm: Update ctr_el0_access for EL2
From: |
Richard Henderson |
Subject: |
[PATCH v4 23/40] target/arm: Update ctr_el0_access for EL2 |
Date: |
Mon, 2 Dec 2019 18:29:20 -0800 |
Update to include checks against HCR_EL2.TID2.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 26 +++++++++++++++++++++-----
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ffa82b5509..9ad5015d5c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5212,11 +5212,27 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
- /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
- * but the AArch32 CTR has its own reginfo struct)
- */
- if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
- return CP_ACCESS_TRAP;
+ int cur_el = arm_current_el(env);
+
+ if (cur_el < 2) {
+ uint64_t hcr = arm_hcr_el2_eff(env);
+
+ if (cur_el == 0) {
+ if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
+ if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ } else {
+ if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
+ return CP_ACCESS_TRAP;
+ }
+ if (hcr & HCR_TID2) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ }
+ } else if (hcr & HCR_TID2) {
+ return CP_ACCESS_TRAP_EL2;
+ }
}
return CP_ACCESS_OK;
}
--
2.17.1
[PATCH v4 21/40] target/arm: Update arm_sctlr for VHE, Richard Henderson, 2019/12/02
[PATCH v4 20/40] target/arm: Update arm_mmu_idx for VHE, Richard Henderson, 2019/12/02
[PATCH v4 23/40] target/arm: Update ctr_el0_access for EL2,
Richard Henderson <=
[PATCH v4 15/40] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits, Richard Henderson, 2019/12/02
[PATCH v4 17/40] target/arm: Tidy ARMMMUIdx m-profile definitions, Richard Henderson, 2019/12/02
[PATCH v4 19/40] target/arm: Add regime_has_2_ranges, Richard Henderson, 2019/12/02
[PATCH v4 22/40] target/arm: Update aa64_zva_access for EL2, Richard Henderson, 2019/12/02
[PATCH v4 29/40] target/arm: Flush tlb for ASID changes in EL2&0 translation regime, Richard Henderson, 2019/12/02