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Re: [PATCH v4 26/40] target/arm: Update define_one_arm_cp_reg_with_opaqu
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From: |
Alex Bennée |
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Subject: |
Re: [PATCH v4 26/40] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE |
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Date: |
Wed, 04 Dec 2019 22:38:57 +0000 |
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User-agent: |
mu4e 1.3.5; emacs 27.0.50 |
Richard Henderson <address@hidden> writes:
> On 12/4/19 10:58 AM, Alex Bennée wrote:
>>> @@ -7437,13 +7437,10 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
>>> mask = PL0_RW;
>>> break;
>>> case 4:
>>> + case 5:
>>> /* min_EL EL2 */
>>> mask = PL2_RW;
>>> break;
>>> - case 5:
>>> - /* unallocated encoding, so not possible */
>>> - assert(false);
>>> - break;
>>
>> This change is fine - I don't think we should have asserted here anyway.
>> But don't we generate an unallocated exception if the CPU is v8.0?
>
> This change is only for validation of the system registers themselves. It has
> nothing to do with the usage of system registers from the actual guest.
So what is the mechanism that feeds back to the translator?
access_check_cp_reg only seems to care about XSCALE. I guess
cp_access_ok would trip if you weren't at EL2 but what if you are a v8.0
at EL2?
--
Alex Bennée
- Re: [PATCH v4 14/40] target/arm: Recover 4 bits from TBFLAGs, (continued)
[PATCH v4 16/40] target/arm: Rearrange ARMMMUIdxBit, Richard Henderson, 2019/12/02
[PATCH v4 26/40] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE, Richard Henderson, 2019/12/02
Re: [PATCH v4 26/40] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE, Peter Maydell, 2019/12/06
[PATCH v4 21/40] target/arm: Update arm_sctlr for VHE, Richard Henderson, 2019/12/02
[PATCH v4 20/40] target/arm: Update arm_mmu_idx for VHE, Richard Henderson, 2019/12/02
[PATCH v4 23/40] target/arm: Update ctr_el0_access for EL2, Richard Henderson, 2019/12/02
[PATCH v4 15/40] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits, Richard Henderson, 2019/12/02
[PATCH v4 17/40] target/arm: Tidy ARMMMUIdx m-profile definitions, Richard Henderson, 2019/12/02