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[PULL 22/34] target/arm: Handle trapping to EL2 of AArch32 VMRS instruct
From: |
Peter Maydell |
Subject: |
[PULL 22/34] target/arm: Handle trapping to EL2 of AArch32 VMRS instructions |
Date: |
Mon, 16 Dec 2019 11:08:52 +0000 |
From: Marc Zyngier <address@hidden>
HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
EL2, and HCR_EL2.TID0 does the same for reads of FPSID.
In order to handle this, introduce a new TCG helper function that
checks for these control bits before executing the VMRC instruction.
Tested with a hacked-up version of KVM/arm64 that sets the control
bits for 32bit guests.
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Marc Zyngier <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[PMM: move helper declaration to helper.h; make it
TCG_CALL_NO_WG]
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.h | 2 ++
target/arm/translate-vfp.inc.c | 20 ++++++++++++++++----
target/arm/vfp_helper.c | 29 +++++++++++++++++++++++++++++
3 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 3d4ec267a2c..7ce5169afb5 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -226,6 +226,8 @@ DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr)
DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env)
DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, ptr)
+DEF_HELPER_FLAGS_3(check_hcr_el2_trap, TCG_CALL_NO_WG, void, env, i32, i32)
+
/* neon_helper.c */
DEF_HELPER_FLAGS_3(neon_qadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(neon_qadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 85c5ef897be..bf90ac0e5b7 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -761,13 +761,25 @@ static bool trans_VMSR_VMRS(DisasContext *s,
arg_VMSR_VMRS *a)
if (a->l) {
/* VMRS, move VFP special register to gp register */
switch (a->reg) {
- case ARM_VFP_FPSID:
- case ARM_VFP_FPEXC:
- case ARM_VFP_FPINST:
- case ARM_VFP_FPINST2:
case ARM_VFP_MVFR0:
case ARM_VFP_MVFR1:
case ARM_VFP_MVFR2:
+ case ARM_VFP_FPSID:
+ if (s->current_el == 1) {
+ TCGv_i32 tcg_reg, tcg_rt;
+
+ gen_set_condexec(s);
+ gen_set_pc_im(s, s->pc_curr);
+ tcg_reg = tcg_const_i32(a->reg);
+ tcg_rt = tcg_const_i32(a->rt);
+ gen_helper_check_hcr_el2_trap(cpu_env, tcg_rt, tcg_reg);
+ tcg_temp_free_i32(tcg_reg);
+ tcg_temp_free_i32(tcg_rt);
+ }
+ /* fall through */
+ case ARM_VFP_FPEXC:
+ case ARM_VFP_FPINST:
+ case ARM_VFP_FPINST2:
tmp = load_cpu_field(vfp.xregs[a->reg]);
break;
case ARM_VFP_FPSCR:
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 9710ef1c3e5..0ae7d4f34a9 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -1322,4 +1322,33 @@ float64 HELPER(frint64_d)(float64 f, void *fpst)
return frint_d(f, fpst, 64);
}
+void HELPER(check_hcr_el2_trap)(CPUARMState *env, uint32_t rt, uint32_t reg)
+{
+ uint32_t syndrome;
+
+ switch (reg) {
+ case ARM_VFP_MVFR0:
+ case ARM_VFP_MVFR1:
+ case ARM_VFP_MVFR2:
+ if (!(arm_hcr_el2_eff(env) & HCR_TID3)) {
+ return;
+ }
+ break;
+ case ARM_VFP_FPSID:
+ if (!(arm_hcr_el2_eff(env) & HCR_TID0)) {
+ return;
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ syndrome = ((EC_FPIDTRAP << ARM_EL_EC_SHIFT)
+ | ARM_EL_IL
+ | (1 << 24) | (0xe << 20) | (7 << 14)
+ | (reg << 10) | (rt << 5) | 1);
+
+ raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);
+}
+
#endif
--
2.20.1
- [PULL 11/34] watchdog/aspeed: Fix AST2600 frequency behaviour, (continued)
- [PULL 11/34] watchdog/aspeed: Fix AST2600 frequency behaviour, Peter Maydell, 2019/12/16
- [PULL 13/34] aspeed/smc: Do not map disabled segment on the AST2600, Peter Maydell, 2019/12/16
- [PULL 14/34] aspeed/smc: Add AST2600 timings registers, Peter Maydell, 2019/12/16
- [PULL 16/34] aspeed: Add support for the tacoma-bmc board, Peter Maydell, 2019/12/16
- [PULL 15/34] aspeed: Remove AspeedBoardConfig array and use AspeedMachineClass, Peter Maydell, 2019/12/16
- [PULL 17/34] gpio: fix memory leak in aspeed_gpio_init(), Peter Maydell, 2019/12/16
- [PULL 18/34] aspeed: Change the "scu" property definition, Peter Maydell, 2019/12/16
- [PULL 19/34] aspeed: Change the "nic" property definition, Peter Maydell, 2019/12/16
- [PULL 20/34] target/arm: Honor HCR_EL2.TID2 trapping requirements, Peter Maydell, 2019/12/16
- [PULL 21/34] target/arm: Honor HCR_EL2.TID1 trapping requirements, Peter Maydell, 2019/12/16
- [PULL 22/34] target/arm: Handle trapping to EL2 of AArch32 VMRS instructions,
Peter Maydell <=
- [PULL 23/34] target/arm: Handle AArch32 CP15 trapping via HSTR_EL2, Peter Maydell, 2019/12/16
- [PULL 24/34] target/arm: Add support for missing Jazelle system registers, Peter Maydell, 2019/12/16
- [PULL 25/34] arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on(), Peter Maydell, 2019/12/16
- [PULL 26/34] tcg: cputlb: Add probe_read, Peter Maydell, 2019/12/16
- [PULL 28/34] migration: ram: Switch to ram block writeback, Peter Maydell, 2019/12/16
- [PULL 29/34] target/arm: Add support for DC CVAP & DC CVADP ins, Peter Maydell, 2019/12/16
- [PULL 30/34] hw/arm/sbsa-ref: Simplify by moving the gic in the machine state, Peter Maydell, 2019/12/16
- [PULL 32/34] hw/arm/acpi: enable SHPC native hot plug, Peter Maydell, 2019/12/16
- [PULL 27/34] Memory: Enable writeback for given memory region, Peter Maydell, 2019/12/16
- [PULL 31/34] hw/arm/acpi: simplify AML bit and/or statement, Peter Maydell, 2019/12/16