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[PULL 24/34] target/arm: Add support for missing Jazelle system register
From: |
Peter Maydell |
Subject: |
[PULL 24/34] target/arm: Add support for missing Jazelle system registers |
Date: |
Mon, 16 Dec 2019 11:08:54 +0000 |
From: Marc Zyngier <address@hidden>
QEMU lacks the minimum Jazelle implementation that is required
by the architecture (everything is RAZ or RAZ/WI). Add it
together with the HCR_EL2.TID0 trapping that goes with it.
Signed-off-by: Marc Zyngier <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[PMM: moved ARMCPRegInfo array to file scope, marked it
'static global', moved new condition down in
register_cp_regs_for_features() to go with other feature
things rather than up with the v6/v7/v8 stuff]
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0ba08d550aa..a4f7b61b4e1 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6040,6 +6040,30 @@ static CPAccessResult access_aa32_tid3(CPUARMState *env,
const ARMCPRegInfo *ri,
return CP_ACCESS_OK;
}
+static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+ if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID0)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+
+ return CP_ACCESS_OK;
+}
+
+static const ARMCPRegInfo jazelle_regs[] = {
+ { .name = "JIDR",
+ .cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0,
+ .access = PL1_R, .accessfn = access_jazelle,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "JOSCR",
+ .cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "JMCR",
+ .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ REGINFO_SENTINEL
+};
+
void register_cp_regs_for_features(ARMCPU *cpu)
{
/* Register all the coprocessor registers based on feature bits */
@@ -6699,6 +6723,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (arm_feature(env, ARM_FEATURE_LPAE)) {
define_arm_cp_regs(cpu, lpae_cp_reginfo);
}
+ if (cpu_isar_feature(jazelle, cpu)) {
+ define_arm_cp_regs(cpu, jazelle_regs);
+ }
/* Slightly awkwardly, the OMAP and StrongARM cores need all of
* cp15 crn=0 to be writes-ignored, whereas for other cores they should
* be read-only (ie write causes UNDEF exception).
--
2.20.1
- [PULL 14/34] aspeed/smc: Add AST2600 timings registers, (continued)
- [PULL 14/34] aspeed/smc: Add AST2600 timings registers, Peter Maydell, 2019/12/16
- [PULL 16/34] aspeed: Add support for the tacoma-bmc board, Peter Maydell, 2019/12/16
- [PULL 15/34] aspeed: Remove AspeedBoardConfig array and use AspeedMachineClass, Peter Maydell, 2019/12/16
- [PULL 17/34] gpio: fix memory leak in aspeed_gpio_init(), Peter Maydell, 2019/12/16
- [PULL 18/34] aspeed: Change the "scu" property definition, Peter Maydell, 2019/12/16
- [PULL 19/34] aspeed: Change the "nic" property definition, Peter Maydell, 2019/12/16
- [PULL 20/34] target/arm: Honor HCR_EL2.TID2 trapping requirements, Peter Maydell, 2019/12/16
- [PULL 21/34] target/arm: Honor HCR_EL2.TID1 trapping requirements, Peter Maydell, 2019/12/16
- [PULL 22/34] target/arm: Handle trapping to EL2 of AArch32 VMRS instructions, Peter Maydell, 2019/12/16
- [PULL 23/34] target/arm: Handle AArch32 CP15 trapping via HSTR_EL2, Peter Maydell, 2019/12/16
- [PULL 24/34] target/arm: Add support for missing Jazelle system registers,
Peter Maydell <=
- [PULL 25/34] arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on(), Peter Maydell, 2019/12/16
- [PULL 26/34] tcg: cputlb: Add probe_read, Peter Maydell, 2019/12/16
- [PULL 28/34] migration: ram: Switch to ram block writeback, Peter Maydell, 2019/12/16
- [PULL 29/34] target/arm: Add support for DC CVAP & DC CVADP ins, Peter Maydell, 2019/12/16
- [PULL 30/34] hw/arm/sbsa-ref: Simplify by moving the gic in the machine state, Peter Maydell, 2019/12/16
- [PULL 32/34] hw/arm/acpi: enable SHPC native hot plug, Peter Maydell, 2019/12/16
- [PULL 27/34] Memory: Enable writeback for given memory region, Peter Maydell, 2019/12/16
- [PULL 31/34] hw/arm/acpi: simplify AML bit and/or statement, Peter Maydell, 2019/12/16
- [PULL 34/34] target/arm: ensure we use current exception state after SCR update, Peter Maydell, 2019/12/16
- [PULL 33/34] hw/arm/virt: Simplify by moving the gic in the machine state, Peter Maydell, 2019/12/16