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[PATCH v7 16/42] target/arm: Implement the STGP instruction
From: |
Richard Henderson |
Subject: |
[PATCH v7 16/42] target/arm: Implement the STGP instruction |
Date: |
Tue, 2 Jun 2020 18:12:51 -0700 |
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v3: Handle atomicity, require pre-cleaned address.
v6: Fix constant offset shift, non-checked address, use pre-computed ata.
---
target/arm/translate-a64.c | 29 ++++++++++++++++++++++++++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 0725c2ca07..2fc070ab90 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -2681,7 +2681,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
* +-----+-------+---+---+-------+---+-------+-------+------+------+
*
* opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
- * LDPSW 01
+ * LDPSW/STGP 01
* LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
* V: 0 -> GPR, 1 -> Vector
* idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
@@ -2706,6 +2706,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t
insn)
bool is_signed = false;
bool postindex = false;
bool wback = false;
+ bool set_tag = false;
TCGv_i64 clean_addr, dirty_addr;
@@ -2718,6 +2719,14 @@ static void disas_ldst_pair(DisasContext *s, uint32_t
insn)
if (is_vector) {
size = 2 + opc;
+ } else if (opc == 1 && !is_load) {
+ /* STGP */
+ if (!dc_isar_feature(aa64_mte_insn_reg, s) || index == 0) {
+ unallocated_encoding(s);
+ return;
+ }
+ size = 3;
+ set_tag = true;
} else {
size = 2 + extract32(opc, 1, 1);
is_signed = extract32(opc, 0, 1);
@@ -2758,7 +2767,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t
insn)
return;
}
- offset <<= size;
+ offset <<= (set_tag ? LOG2_TAG_GRANULE : size);
if (rn == 31) {
gen_check_sp_alignment(s);
@@ -2768,8 +2777,22 @@ static void disas_ldst_pair(DisasContext *s, uint32_t
insn)
if (!postindex) {
tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
}
- clean_addr = clean_data_tbi(s, dirty_addr);
+ if (set_tag) {
+ if (!s->ata) {
+ /*
+ * TODO: We could rely on the stores below, at least for
+ * system mode, if we arrange to add MO_ALIGN_16.
+ */
+ gen_helper_stg_stub(cpu_env, dirty_addr);
+ } else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
+ gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr);
+ } else {
+ gen_helper_stg(cpu_env, dirty_addr, dirty_addr);
+ }
+ }
+
+ clean_addr = clean_data_tbi(s, dirty_addr);
if (is_vector) {
if (is_load) {
do_fp_ld(s, rt, clean_addr, size);
--
2.25.1
- Re: [PATCH v7 10/42] target/arm: Implement the ADDG, SUBG instructions, (continued)
[PATCH v7 11/42] target/arm: Implement the GMI instruction, Richard Henderson, 2020/06/02
[PATCH v7 12/42] target/arm: Implement the SUBP instruction, Richard Henderson, 2020/06/02
[PATCH v7 13/42] target/arm: Define arm_cpu_do_unaligned_access for user-only, Richard Henderson, 2020/06/02
[PATCH v7 16/42] target/arm: Implement the STGP instruction,
Richard Henderson <=
[PATCH v7 17/42] target/arm: Restrict the values of DCZID.BS under TCG, Richard Henderson, 2020/06/02
[PATCH v7 14/42] target/arm: Add helper_probe_access, Richard Henderson, 2020/06/02
[PATCH v7 21/42] target/arm: Move regime_el to internals.h, Richard Henderson, 2020/06/02
[PATCH v7 15/42] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2020/06/02