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[PATCH v2 00/17] RISC-V: Update the Hypervisor spec to v0.6.1
From: |
Alistair Francis |
Subject: |
[PATCH v2 00/17] RISC-V: Update the Hypervisor spec to v0.6.1 |
Date: |
Thu, 4 Jun 2020 18:20:42 -0700 |
From: Alistair Francis <alistair@alistair23.me>
This series updates the experimental QEMU RISC-V Hypervisor spec to the
v0.6.1 draft implementation.
THis includes support for the new 2-stage lookup instructions and the new
CSRs.
It also includes the new 0.6.1 support for the virtual instruction
fault.
This was tested by running 32-bit and 64-bit Xvisor on QEMU and starting
Linux guests.
v2:
- Update to v0.6.1
Alistair Francis (17):
target/riscv: Set access as data_load when validating stage-2 PTEs
target/riscv: Report errors validating 2nd-stage PTEs
target/riscv: Move the hfence instructions to the rvh decode
target/riscv: Implement checks for hfence
target/riscv: Allow setting a two-stage lookup in the virt status
target/riscv: Allow generating hlv/hlvx/hsv instructions
target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
target/riscv: Don't allow guest to write to htinst
target/riscv: Convert MSTATUS MTL to GVA
target/riscv: Fix the interrupt cause code
target/riscv: Update the Hypervisor trap return/entry
target/riscv: Update the CSRs to the v0.6 Hyp extension
target/riscv: Only support a single VSXL length
target/riscv: Only support little endian guests
target/riscv: Support the v0.6 Hypervisor extension CRSs
target/riscv: Return the exception from invalid CSR accesses
target/riscv: Support the Virtual Instruction fault
target/riscv/cpu.h | 2 +
target/riscv/cpu_bits.h | 25 +-
target/riscv/helper.h | 9 +
target/riscv/insn32-64.decode | 5 +
target/riscv/insn32.decode | 19 +-
target/riscv/cpu_helper.c | 114 +++---
target/riscv/csr.c | 171 ++++++--
.../riscv/insn_trans/trans_privileged.inc.c | 38 --
target/riscv/insn_trans/trans_rvh.inc.c | 377 ++++++++++++++++++
target/riscv/op_helper.c | 189 ++++++++-
target/riscv/translate.c | 11 +-
11 files changed, 815 insertions(+), 145 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvh.inc.c
--
2.26.2
- [PATCH v2 00/17] RISC-V: Update the Hypervisor spec to v0.6.1,
Alistair Francis <=
- [PATCH v2 01/17] target/riscv: Set access as data_load when validating stage-2 PTEs, Alistair Francis, 2020/06/04
- [PATCH v2 02/17] target/riscv: Report errors validating 2nd-stage PTEs, Alistair Francis, 2020/06/04
- [PATCH v2 03/17] target/riscv: Move the hfence instructions to the rvh decode, Alistair Francis, 2020/06/04
- [PATCH v2 04/17] target/riscv: Implement checks for hfence, Alistair Francis, 2020/06/04
- [PATCH v2 05/17] target/riscv: Allow setting a two-stage lookup in the virt status, Alistair Francis, 2020/06/04
- [PATCH v2 11/17] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/06/04