[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH rc1 03/15] hw/sh4: Use MemoryRegion typedef
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH rc1 03/15] hw/sh4: Use MemoryRegion typedef |
Date: |
Wed, 17 Jun 2020 21:15:07 +0200 |
Use the MemoryRegion type defined in "qemu/typedefs.h",
to keep the repository style consistent.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/sh4/sh.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h
index 767a2df7e2..fe773cb01d 100644
--- a/include/hw/sh4/sh.h
+++ b/include/hw/sh4/sh.h
@@ -10,9 +10,8 @@
/* sh7750.c */
struct SH7750State;
-struct MemoryRegion;
-struct SH7750State *sh7750_init(SuperHCPU *cpu, struct MemoryRegion *sysmem);
+struct SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem);
typedef struct {
/* The callback will be triggered if any of the designated lines change */
@@ -32,7 +31,7 @@ int sh7750_register_io_device(struct SH7750State *s,
#define TMU012_FEAT_TOCR (1 << 0)
#define TMU012_FEAT_3CHAN (1 << 1)
#define TMU012_FEAT_EXTCLK (1 << 2)
-void tmu012_init(struct MemoryRegion *sysmem, hwaddr base,
+void tmu012_init(MemoryRegion *sysmem, hwaddr base,
int feat, uint32_t freq,
qemu_irq ch0_irq, qemu_irq ch1_irq,
qemu_irq ch2_irq0, qemu_irq ch2_irq1);
--
2.21.3
- [PATCH rc1 00/15] hw: Renesas patches (SH4 and RX), Philippe Mathieu-Daudé, 2020/06/17
- [PATCH rc1 01/15] MAINTAINERS: Cover sh_intc files in the R2D/Shix machine sections, Philippe Mathieu-Daudé, 2020/06/17
- [PATCH rc1 02/15] MAINTAINERS: Add an entry for common Renesas peripherals, Philippe Mathieu-Daudé, 2020/06/17
- [PATCH rc1 03/15] hw/sh4: Use MemoryRegion typedef,
Philippe Mathieu-Daudé <=
- [PATCH rc1 05/15] hw/timer/sh_timer: Remove unused 'qemu/timer.h' include, Philippe Mathieu-Daudé, 2020/06/17
- [PATCH rc1 04/15] hw/sh4: Extract timer definitions to 'hw/timer/tmu012.h', Philippe Mathieu-Daudé, 2020/06/17
- [PATCH rc1 06/15] hw/intc: RX62N interrupt controller (ICUa), Philippe Mathieu-Daudé, 2020/06/17
- [PATCH rc1 07/15] hw/timer: RX62N 8-Bit timer (TMR), Philippe Mathieu-Daudé, 2020/06/17
- [PATCH rc1 08/15] hw/timer: RX62N compare match timer (CMT), Philippe Mathieu-Daudé, 2020/06/17
- [PATCH rc1 09/15] hw/char: RX62N serial communication interface (SCI), Philippe Mathieu-Daudé, 2020/06/17
- [PATCH rc1 11/15] hw/rx: Honor -accel qtest, Philippe Mathieu-Daudé, 2020/06/17
- [PATCH rc1 10/15] hw/rx: RX62N microcontroller (MCU), Philippe Mathieu-Daudé, 2020/06/17
- [PATCH rc1 12/15] hw/rx: Register R5F562N7 and R5F562N8 MCUs, Philippe Mathieu-Daudé, 2020/06/17