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[PATCH v10 51/61] target/riscv: vmfirst find-first-set mask bit
From: |
LIU Zhiwei |
Subject: |
[PATCH v10 51/61] target/riscv: vmfirst find-first-set mask bit |
Date: |
Sat, 20 Jun 2020 12:36:51 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 32 +++++++++++++++++++++++++
target/riscv/vector_helper.c | 19 +++++++++++++++
4 files changed, 54 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index abae503b9c..28aeb74f43 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1103,3 +1103,5 @@ DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env,
i32)
DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_4(vmpopc_m, tl, ptr, ptr, env, i32)
+
+DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 971c06c09e..a0f3315dbc 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -556,6 +556,7 @@ vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
vmpopc_m 010100 . ..... ----- 010 ..... 1010111 @r2_vm
+vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index d1c8c6a11f..735ae8377e 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2421,3 +2421,35 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
}
return false;
}
+
+/* vmfirst find-first-set mask bit */
+static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
+{
+ if (vext_check_isa_ill(s)) {
+ TCGv_ptr src2, mask;
+ TCGv dst;
+ TCGv_i32 desc;
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+
+ mask = tcg_temp_new_ptr();
+ src2 = tcg_temp_new_ptr();
+ dst = tcg_temp_new();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+
+ tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
+ tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+
+ gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc);
+ gen_set_gpr(a->rd, dst);
+
+ tcg_temp_free_ptr(mask);
+ tcg_temp_free_ptr(src2);
+ tcg_temp_free(dst);
+ tcg_temp_free_i32(desc);
+ return true;
+ }
+ return false;
+}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index f572388981..d178ed4c0b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4562,3 +4562,22 @@ target_ulong HELPER(vmpopc_m)(void *v0, void *vs2,
CPURISCVState *env,
}
return cnt;
}
+
+/* vmfirst find-first-set mask bit*/
+target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env,
+ uint32_t desc)
+{
+ uint32_t mlen = vext_mlen(desc);
+ uint32_t vm = vext_vm(desc);
+ uint32_t vl = env->vl;
+ int i;
+
+ for (i = 0; i < vl; i++) {
+ if (vm || vext_elem_mask(v0, mlen, i)) {
+ if (vext_elem_mask(vs2, mlen, i)) {
+ return i;
+ }
+ }
+ }
+ return -1LL;
+}
--
2.23.0
- [PATCH v10 41/61] target/riscv: vector floating-point merge instructions, (continued)
- [PATCH v10 41/61] target/riscv: vector floating-point merge instructions, LIU Zhiwei, 2020/06/20
- [PATCH v10 42/61] target/riscv: vector floating-point/integer type-convert instructions, LIU Zhiwei, 2020/06/20
- [PATCH v10 43/61] target/riscv: widening floating-point/integer type-convert instructions, LIU Zhiwei, 2020/06/20
- [PATCH v10 44/61] target/riscv: narrowing floating-point/integer type-convert instructions, LIU Zhiwei, 2020/06/20
- [PATCH v10 45/61] target/riscv: vector single-width integer reduction instructions, LIU Zhiwei, 2020/06/20
- [PATCH v10 46/61] target/riscv: vector wideing integer reduction instructions, LIU Zhiwei, 2020/06/20
- [PATCH v10 47/61] target/riscv: vector single-width floating-point reduction instructions, LIU Zhiwei, 2020/06/20
- [PATCH v10 48/61] target/riscv: vector widening floating-point reduction instructions, LIU Zhiwei, 2020/06/20
- [PATCH v10 49/61] target/riscv: vector mask-register logical instructions, LIU Zhiwei, 2020/06/20
- [PATCH v10 50/61] target/riscv: vector mask population count vmpopc, LIU Zhiwei, 2020/06/20
- [PATCH v10 51/61] target/riscv: vmfirst find-first-set mask bit,
LIU Zhiwei <=
- [PATCH v10 52/61] target/riscv: set-X-first mask bit, LIU Zhiwei, 2020/06/20
- [PATCH v10 53/61] target/riscv: vector iota instruction, LIU Zhiwei, 2020/06/20
- [PATCH v10 54/61] target/riscv: vector element index instruction, LIU Zhiwei, 2020/06/20
- [PATCH v10 55/61] target/riscv: integer extract instruction, LIU Zhiwei, 2020/06/20
- [PATCH v10 56/61] target/riscv: integer scalar move instruction, LIU Zhiwei, 2020/06/20
- [PATCH v10 57/61] target/riscv: floating-point scalar move instructions, LIU Zhiwei, 2020/06/20
- [PATCH v10 58/61] target/riscv: vector slide instructions, LIU Zhiwei, 2020/06/20
- [PATCH v10 59/61] target/riscv: vector register gather instruction, LIU Zhiwei, 2020/06/20
- [PATCH v10 60/61] target/riscv: vector compress instruction, LIU Zhiwei, 2020/06/20
- [PATCH v10 61/61] target/riscv: configure and turn on vector extension from command line, LIU Zhiwei, 2020/06/20