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[PULL 07/20] aspeed/sdhci: Fix reset sequence
From: |
Cédric Le Goater |
Subject: |
[PULL 07/20] aspeed/sdhci: Fix reset sequence |
Date: |
Tue, 1 Sep 2020 14:45:12 +0200 |
BIT(0) of the ASPEED_SDHCI_INFO register is set by SW and polled until
the bit is cleared by HW.
Use the number of supported slots to define the default value of this
register (The AST2600 eMMC Controller only has one). Fix the reset
sequence by clearing automatically the RESET bit.
Cc: Eddie James <eajames@linux.ibm.com>
Fixes: 2bea128c3d0b ("hw/sd/aspeed_sdhci: New device")
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20200819100956.2216690-9-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/sd/aspeed_sdhci.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
index 22cafce0fbdc..4f24b7d2f942 100644
--- a/hw/sd/aspeed_sdhci.c
+++ b/hw/sd/aspeed_sdhci.c
@@ -16,7 +16,9 @@
#include "hw/qdev-properties.h"
#define ASPEED_SDHCI_INFO 0x00
-#define ASPEED_SDHCI_INFO_RESET 0x00030000
+#define ASPEED_SDHCI_INFO_SLOT1 (1 << 17)
+#define ASPEED_SDHCI_INFO_SLOT0 (1 << 16)
+#define ASPEED_SDHCI_INFO_RESET (1 << 0)
#define ASPEED_SDHCI_DEBOUNCE 0x04
#define ASPEED_SDHCI_DEBOUNCE_RESET 0x00000005
#define ASPEED_SDHCI_BUS 0x08
@@ -67,6 +69,10 @@ static void aspeed_sdhci_write(void *opaque, hwaddr addr,
uint64_t val,
AspeedSDHCIState *sdhci = opaque;
switch (addr) {
+ case ASPEED_SDHCI_INFO:
+ /* The RESET bit automatically clears. */
+ sdhci->regs[TO_REG(addr)] = (uint32_t)val & ~ASPEED_SDHCI_INFO_RESET;
+ break;
case ASPEED_SDHCI_SDIO_140:
sdhci->slots[0].capareg = (uint64_t)(uint32_t)val;
break;
@@ -155,7 +161,11 @@ static void aspeed_sdhci_reset(DeviceState *dev)
AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);
memset(sdhci->regs, 0, ASPEED_SDHCI_REG_SIZE);
- sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] = ASPEED_SDHCI_INFO_RESET;
+
+ sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] = ASPEED_SDHCI_INFO_SLOT0;
+ if (sdhci->num_slots == 2) {
+ sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] |= ASPEED_SDHCI_INFO_SLOT1;
+ }
sdhci->regs[TO_REG(ASPEED_SDHCI_DEBOUNCE)] = ASPEED_SDHCI_DEBOUNCE_RESET;
}
--
2.25.4
- [PULL 00/20] aspeed queue, Cédric Le Goater, 2020/09/01
- [PULL 06/20] aspeed/smc: Fix max_slaves of the legacy SMC device, Cédric Le Goater, 2020/09/01
- [PULL 02/20] m25p80: Add support for n25q512ax3, Cédric Le Goater, 2020/09/01
- [PULL 12/20] ftgmac100: Check for invalid len and address before doing a DMA transfer, Cédric Le Goater, 2020/09/01
- [PULL 01/20] m25p80: Return the JEDEC ID twice for mx25l25635e, Cédric Le Goater, 2020/09/01
- [PULL 05/20] aspeed/smc: Fix MemoryRegionOps definition, Cédric Le Goater, 2020/09/01
- [PULL 07/20] aspeed/sdhci: Fix reset sequence,
Cédric Le Goater <=
- [PULL 03/20] aspeed/scu: Fix valid access size on AST2400, Cédric Le Goater, 2020/09/01
- [PULL 08/20] ftgmac100: Fix registers that can be read, Cédric Le Goater, 2020/09/01
- [PULL 04/20] hw/arm/aspeed: Add board model for Supermicro X11 BMC, Cédric Le Goater, 2020/09/01
- [PULL 15/20] aspeed/sdmc: Perform memory training, Cédric Le Goater, 2020/09/01
- [PULL 16/20] aspeed/sdmc: Allow writes to unprotected registers, Cédric Le Goater, 2020/09/01
- [PULL 14/20] ftgmac100: Improve software reset, Cédric Le Goater, 2020/09/01
- [PULL 09/20] ftgmac100: Fix interrupt status "Packet transmitted on ethernet", Cédric Le Goater, 2020/09/01
- [PULL 18/20] aspeed/smc: Open AHB window of the second chip of the AST2600 FMC controller, Cédric Le Goater, 2020/09/01
- [PULL 20/20] hw: add a number of SPI-flash's of m25p80 family, Cédric Le Goater, 2020/09/01
- [PULL 10/20] ftgmac100: Fix interrupt status "Packet moved to RX FIFO", Cédric Le Goater, 2020/09/01