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[PULL 16/20] aspeed/sdmc: Allow writes to unprotected registers
From: |
Cédric Le Goater |
Subject: |
[PULL 16/20] aspeed/sdmc: Allow writes to unprotected registers |
Date: |
Tue, 1 Sep 2020 14:45:21 +0200 |
From: Joel Stanley <joel@jms.id.au>
A subset of registers are not protected by the lock behaviour, so allow
unconditionally writing to those.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20200819100956.2216690-18-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/misc/aspeed_sdmc.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index ff2809a09965..81c73450ab5d 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -33,15 +33,28 @@
/* Configuration Register */
#define R_CONF (0x04 / 4)
+/* Interrupt control/status */
+#define R_ISR (0x50 / 4)
+
/* Control/Status Register #1 (ast2500) */
#define R_STATUS1 (0x60 / 4)
#define PHY_BUSY_STATE BIT(0)
#define PHY_PLL_LOCK_STATUS BIT(4)
+/* Reserved */
+#define R_MCR6C (0x6c / 4)
+
#define R_ECC_TEST_CTRL (0x70 / 4)
#define ECC_TEST_FINISHED BIT(12)
#define ECC_TEST_FAIL BIT(13)
+#define R_TEST_START_LEN (0x74 / 4)
+#define R_TEST_FAIL_DQ (0x78 / 4)
+#define R_TEST_INIT_VAL (0x7c / 4)
+#define R_DRAM_SW (0x88 / 4)
+#define R_DRAM_TIME (0x8c / 4)
+#define R_ECC_ERR_INJECT (0xb4 / 4)
+
/*
* Configuration register Ox4 (for Aspeed AST2400 SOC)
*
@@ -449,6 +462,20 @@ static uint32_t
aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,
uint32_t data)
{
+ /* Unprotected registers */
+ switch (reg) {
+ case R_ISR:
+ case R_MCR6C:
+ case R_TEST_START_LEN:
+ case R_TEST_FAIL_DQ:
+ case R_TEST_INIT_VAL:
+ case R_DRAM_SW:
+ case R_DRAM_TIME:
+ case R_ECC_ERR_INJECT:
+ s->regs[reg] = data;
+ return;
+ }
+
if (s->regs[R_PROT] == PROT_HARDLOCKED) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system
reset!\n",
__func__);
--
2.25.4
- [PULL 06/20] aspeed/smc: Fix max_slaves of the legacy SMC device, (continued)
- [PULL 06/20] aspeed/smc: Fix max_slaves of the legacy SMC device, Cédric Le Goater, 2020/09/01
- [PULL 02/20] m25p80: Add support for n25q512ax3, Cédric Le Goater, 2020/09/01
- [PULL 12/20] ftgmac100: Check for invalid len and address before doing a DMA transfer, Cédric Le Goater, 2020/09/01
- [PULL 01/20] m25p80: Return the JEDEC ID twice for mx25l25635e, Cédric Le Goater, 2020/09/01
- [PULL 05/20] aspeed/smc: Fix MemoryRegionOps definition, Cédric Le Goater, 2020/09/01
- [PULL 07/20] aspeed/sdhci: Fix reset sequence, Cédric Le Goater, 2020/09/01
- [PULL 03/20] aspeed/scu: Fix valid access size on AST2400, Cédric Le Goater, 2020/09/01
- [PULL 08/20] ftgmac100: Fix registers that can be read, Cédric Le Goater, 2020/09/01
- [PULL 04/20] hw/arm/aspeed: Add board model for Supermicro X11 BMC, Cédric Le Goater, 2020/09/01
- [PULL 15/20] aspeed/sdmc: Perform memory training, Cédric Le Goater, 2020/09/01
- [PULL 16/20] aspeed/sdmc: Allow writes to unprotected registers,
Cédric Le Goater <=
- [PULL 14/20] ftgmac100: Improve software reset, Cédric Le Goater, 2020/09/01
- [PULL 09/20] ftgmac100: Fix interrupt status "Packet transmitted on ethernet", Cédric Le Goater, 2020/09/01
- [PULL 18/20] aspeed/smc: Open AHB window of the second chip of the AST2600 FMC controller, Cédric Le Goater, 2020/09/01
- [PULL 20/20] hw: add a number of SPI-flash's of m25p80 family, Cédric Le Goater, 2020/09/01
- [PULL 10/20] ftgmac100: Fix interrupt status "Packet moved to RX FIFO", Cédric Le Goater, 2020/09/01
- [PULL 13/20] ftgmac100: Fix integer overflow in ftgmac100_do_tx(), Cédric Le Goater, 2020/09/01
- [PULL 19/20] arm: aspeed: add strap define `25HZ` of AST2500, Cédric Le Goater, 2020/09/01
- [PULL 17/20] aspeed/sdmc: Simplify calculation of RAM bits, Cédric Le Goater, 2020/09/01
- [PULL 11/20] ftgmac100: Change interrupt status when a DMA error occurs, Cédric Le Goater, 2020/09/01
- Re: [PULL 00/20] aspeed queue, Peter Maydell, 2020/09/03