[PATCH 00/12] hw/riscv: Clean up the directory

[Bin Meng]

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Peripheral models for a specific SoC are moved to its
corresponding hw/* subdirectories.

This series should be applied after the PolarFire SoC series:
http://patchwork.ozlabs.org/project/qemu-devel/list/?series=198727


Bin Meng (12):
  hw/riscv: Move sifive_e_prci model to hw/misc
  hw/riscv: Move sifive_u_prci model to hw/misc
  hw/riscv: Move sifive_u_otp model to hw/misc
  hw/riscv: Move sifive_gpio model to hw/gpio
  hw/riscv: Move sifive_clint model to hw/intc
  hw/riscv: Move sifive_plic model to hw/intc
  hw/riscv: Move riscv_htif model to hw/char
  hw/riscv: Move sifive_uart model to hw/char
  hw/riscv: Move sifive_test model to hw/misc
  hw/riscv: Always build riscv_hart.c
  hw/riscv: Drop CONFIG_SIFIVE
  hw/riscv: Sort the Kconfig options in alphabetical order

 {include/hw/riscv => hw/intc}/sifive_plic.h |  0
 hw/riscv/trace.h                            |  1 -
 include/hw/{riscv => char}/riscv_htif.h     |  0
 include/hw/{riscv => char}/sifive_uart.h    |  0
 include/hw/{riscv => gpio}/sifive_gpio.h    |  0
 include/hw/{riscv => intc}/sifive_clint.h   |  0
 include/hw/{riscv => misc}/sifive_e_prci.h  |  0
 include/hw/{riscv => misc}/sifive_test.h    |  0
 include/hw/{riscv => misc}/sifive_u_otp.h   |  0
 include/hw/{riscv => misc}/sifive_u_prci.h  |  0
 include/hw/riscv/sifive_e.h                 |  2 +-
 include/hw/riscv/sifive_u.h                 |  6 +--
 hw/{riscv => char}/riscv_htif.c             |  2 +-
 hw/{riscv => char}/sifive_uart.c            |  2 +-
 hw/{riscv => gpio}/sifive_gpio.c            |  2 +-
 hw/{riscv => intc}/sifive_clint.c           |  2 +-
 hw/{riscv => intc}/sifive_plic.c            |  2 +-
 hw/{riscv => misc}/sifive_e_prci.c          |  2 +-
 hw/{riscv => misc}/sifive_test.c            |  2 +-
 hw/{riscv => misc}/sifive_u_otp.c           |  2 +-
 hw/{riscv => misc}/sifive_u_prci.c          |  2 +-
 hw/riscv/microchip_pfsoc.c                  |  4 +-
 hw/riscv/sifive_e.c                         |  8 ++--
 hw/riscv/sifive_u.c                         |  6 +--
 hw/riscv/spike.c                            |  4 +-
 hw/riscv/virt.c                             |  6 +--
 hw/char/Kconfig                             |  6 +++
 hw/char/meson.build                         |  2 +
 hw/gpio/Kconfig                             |  3 ++
 hw/gpio/meson.build                         |  1 +
 hw/gpio/trace-events                        |  6 +++
 hw/intc/Kconfig                             |  6 +++
 hw/intc/meson.build                         |  2 +
 hw/misc/Kconfig                             | 12 +++++
 hw/misc/meson.build                         |  6 +++
 hw/riscv/Kconfig                            | 74 +++++++++++++++--------------
 hw/riscv/meson.build                        | 11 +----
 hw/riscv/trace-events                       |  7 ---
 meson.build                                 |  1 -
 39 files changed, 110 insertions(+), 82 deletions(-)
 rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
 delete mode 100644 hw/riscv/trace.h
 rename include/hw/{riscv => char}/riscv_htif.h (100%)
 rename include/hw/{riscv => char}/sifive_uart.h (100%)
 rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
 rename include/hw/{riscv => intc}/sifive_clint.h (100%)
 rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
 rename include/hw/{riscv => misc}/sifive_test.h (100%)
 rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
 rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
 rename hw/{riscv => char}/riscv_htif.c (99%)
 rename hw/{riscv => char}/sifive_uart.c (99%)
 rename hw/{riscv => gpio}/sifive_gpio.c (99%)
 rename hw/{riscv => intc}/sifive_clint.c (99%)
 rename hw/{riscv => intc}/sifive_plic.c (99%)
 rename hw/{riscv => misc}/sifive_e_prci.c (99%)
 rename hw/{riscv => misc}/sifive_test.c (98%)
 rename hw/{riscv => misc}/sifive_u_otp.c (99%)
 rename hw/{riscv => misc}/sifive_u_prci.c (99%)
 delete mode 100644 hw/riscv/trace-events

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2.7.4