Re: [PATCH 03/12] hw/riscv: Move sifive_u_otp model to hw/misc

[Alistair Francis]

On Thu, Sep 3, 2020 at 3:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_u_otp model to hw/misc directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  include/hw/{riscv => misc}/sifive_u_otp.h | 0
>  include/hw/riscv/sifive_u.h               | 2 +-
>  hw/{riscv => misc}/sifive_u_otp.c         | 2 +-
>  hw/misc/Kconfig                           | 3 +++
>  hw/misc/meson.build                       | 1 +
>  hw/riscv/Kconfig                          | 1 +
>  hw/riscv/meson.build                      | 1 -
>  7 files changed, 7 insertions(+), 3 deletions(-)
>  rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
>  rename hw/{riscv => misc}/sifive_u_otp.c (99%)
>
> diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h
> similarity index 100%
> rename from include/hw/riscv/sifive_u_otp.h
> rename to include/hw/misc/sifive_u_otp.h
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index cbeb228..936a3bd 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -24,7 +24,7 @@
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_cpu.h"
>  #include "hw/riscv/sifive_gpio.h"
> -#include "hw/riscv/sifive_u_otp.h"
> +#include "hw/misc/sifive_u_otp.h"
>  #include "hw/misc/sifive_u_prci.h"
>
>  #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
> diff --git a/hw/riscv/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
> similarity index 99%
> rename from hw/riscv/sifive_u_otp.c
> rename to hw/misc/sifive_u_otp.c
> index f6ecbaa..c2f3c8e 100644
> --- a/hw/riscv/sifive_u_otp.c
> +++ b/hw/misc/sifive_u_otp.c
> @@ -23,7 +23,7 @@
>  #include "hw/sysbus.h"
>  #include "qemu/log.h"
>  #include "qemu/module.h"
> -#include "hw/riscv/sifive_u_otp.h"
> +#include "hw/misc/sifive_u_otp.h"
>
>  static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int 
> size)
>  {
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index 65f3fdd..fa3d0f4 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -137,6 +137,9 @@ config AVR_POWER
>  config SIFIVE_E_PRCI
>      bool
>
> +config SIFIVE_U_OTP
> +    bool
> +
>  config SIFIVE_U_PRCI
>      bool
>
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index 9e9550e..018a88c 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -23,6 +23,7 @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: 
> files('mos6522.c'))
>
>  # RISC-V devices
>  softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: 
> files('sifive_e_prci.c'))
> +softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
>  softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: 
> files('sifive_u_prci.c'))
>
>  # PKUnity SoC devices
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 109364b..76eaf77 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -24,6 +24,7 @@ config SIFIVE_U
>      select HART
>      select SIFIVE
>      select SIFIVE_PDMA
> +    select SIFIVE_U_OTP
>      select SIFIVE_U_PRCI
>      select UNIMP
>
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index e6c8af0..2ba4757 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -11,7 +11,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: 
> files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
>  riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: 
> files('microchip_pfsoc.c'))
> --
> 2.7.4
>
>