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Re: [PATCH 5/5] target/arm: Make isar_feature_aa32_fp16_arith() handle M
From: |
Richard Henderson |
Subject: |
Re: [PATCH 5/5] target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile |
Date: |
Fri, 11 Sep 2020 12:32:23 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 9/10/20 10:38 AM, Peter Maydell wrote:
> +static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
> +{
> + return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
> +}
> +
> static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
> {
> - return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
> + /* Sadly this is encoded differently for A-profile and M-profile */
> + if (isar_feature_aa32_mprofile(id)) {
> + return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
> + } else {
> + return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
> + }
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
- [PATCH 0/5] handle M-profile in fp16_arith isar_feature test, Peter Maydell, 2020/09/10
- [PATCH 2/5] target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters, Peter Maydell, 2020/09/10
- [PATCH 1/5] target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check, Peter Maydell, 2020/09/10
- [PATCH 3/5] hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs, Peter Maydell, 2020/09/10
- [PATCH 5/5] target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile, Peter Maydell, 2020/09/10
- Re: [PATCH 5/5] target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile,
Richard Henderson <=
- [PATCH 4/5] target/arm: Add ID register values for Cortex-M0, Peter Maydell, 2020/09/10
- Re: [PATCH 0/5] handle M-profile in fp16_arith isar_feature test, Richard Henderson, 2020/09/11