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[RFC PATCH 18/19] target/mips: Restrict some TCG specific CPUClass handl
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[RFC PATCH 18/19] target/mips: Restrict some TCG specific CPUClass handlers |
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Date: |
Mon, 7 Dec 2020 00:39:48 +0100 |
Restrict the following CPUClass handlers to TCG:
- do_interrupt
- do_transaction_failed
- do_unaligned_access
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
Cc: Claudio Fontana <cfontana@suse.de>
target/mips/cpu.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 8a4486e3ea1..03bd35b7903 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -483,7 +483,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = mips_cpu_class_by_name;
cc->has_work = mips_cpu_has_work;
- cc->do_interrupt = mips_cpu_do_interrupt;
cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->dump_state = mips_cpu_dump_state;
cc->set_pc = mips_cpu_set_pc;
@@ -491,8 +490,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = mips_cpu_do_transaction_failed;
- cc->do_unaligned_access = mips_cpu_do_unaligned_access;
+ cc->do_interrupt = mips_cpu_do_interrupt;
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_mips_cpu;
#endif
@@ -500,6 +498,10 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
#ifdef CONFIG_TCG
cc->tcg_initialize = mips_tcg_init;
cc->tlb_fill = mips_cpu_tlb_fill;
+#if !defined(CONFIG_USER_ONLY)
+ cc->do_unaligned_access = mips_cpu_do_unaligned_access;
+ cc->do_transaction_failed = mips_cpu_do_transaction_failed;
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
#endif
cc->gdb_num_core_regs = 73;
--
2.26.2
- Re: [PATCH 14/19] target/mips: Move mmu_init() functions to tlb_helper.c, (continued)
- [PATCH 12/19] target/mips: Rename helper.c as tlb_helper.c, Philippe Mathieu-Daudé, 2020/12/06
- [PATCH 15/19] target/mips: Move cpu definitions, reset() and realize() to cpu.c, Philippe Mathieu-Daudé, 2020/12/06
- [PATCH 16/19] target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn(), Philippe Mathieu-Daudé, 2020/12/06
- [PATCH 17/19] target/mips: Rename translate_init.c as cpu-defs.c, Philippe Mathieu-Daudé, 2020/12/06
- [RFC PATCH 18/19] target/mips: Restrict some TCG specific CPUClass handlers,
Philippe Mathieu-Daudé <=
[RFC PATCH 19/19] target/mips: Only build TCG code when CONFIG_TCG is set, Philippe Mathieu-Daudé, 2020/12/06
Re: [PATCH 00/19] target/mips: Boring code reordering, no-reply, 2020/12/06