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[PATCH 06/17] target/mips: Alias MSA vector registers on FPU scalar regi
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[PATCH 06/17] target/mips: Alias MSA vector registers on FPU scalar registers |
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Date: |
Tue, 8 Dec 2020 01:36:51 +0100 |
Commits 863f264d10f ("add msa_reset(), global msa register") and
cb269f273fd ("fix multiple TCG registers covering same data")
removed the FPU scalar registers and replaced them by aliases to
the MSA vector registers.
While this might be the case for CPU implementing MSA, this makes
QEMU code incoherent for CPU not implementing it. It is simpler
to inverse the logic and alias the MSA vector registers on the
FPU scalar ones.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index da0cb98df09..95d07e837c0 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31561,16 +31561,20 @@ void mips_tcg_init(void)
offsetof(CPUMIPSState,
active_tc.gpr[i]),
regnames[i]);
-
for (i = 0; i < 32; i++) {
int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
- msa_wr_d[i * 2] =
- tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2]);
+
+ fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]);
+ }
+ /* MSA */
+ for (i = 0; i < 32; i++) {
+ int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
+
/*
- * The scalar floating-point unit (FPU) registers are mapped on
- * the MSA vector registers.
+ * The MSA vector registers are mapped on the
+ * scalar floating-point unit (FPU) registers.
*/
- fpu_f64[i] = msa_wr_d[i * 2];
+ msa_wr_d[i * 2] = fpu_f64[i];
off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
msa_wr_d[i * 2 + 1] =
tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
--
2.26.2
- [PATCH 00/17] target/mips: Convert MSA ASE to decodetree, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 01/17] target/mips: Introduce ase_msa_available() helper, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 02/17] target/mips: Simplify msa_reset(), Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 03/17] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 04/17] target/mips: Simplify MSA TCG logic, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 05/17] target/mips: Remove now unused ASE_MSA definition, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 06/17] target/mips: Alias MSA vector registers on FPU scalar registers,
Philippe Mathieu-Daudé <=
- [PATCH 07/17] target/mips: Extract msa_translate_init() from mips_tcg_init(), Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 08/17] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 09/17] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ(), Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 10/17] target/mips: Rename msa_helper.c as mod-msa_helper.c, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 11/17] target/mips: Move msa_reset() to mod-msa_helper.c, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 12/17] target/mips: Extract MSA helpers from op_helper.c, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 14/17] target/mips: Declare gen_msa/_branch() in 'translate.h', Philippe Mathieu-Daudé, 2020/12/07