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[PATCH 11/17] target/mips: Move msa_reset() to mod-msa_helper.c
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[PATCH 11/17] target/mips: Move msa_reset() to mod-msa_helper.c |
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Date: |
Tue, 8 Dec 2020 01:36:56 +0100 |
translate_init.c.inc mostly contains CPU definitions.
msa_reset() doesn't belong here, move it with the MSA
helpers.
One comment style is updated to avoid checkpatch.pl warning.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/internal.h | 2 ++
target/mips/mod-msa_helper.c | 36 ++++++++++++++++++++++++++++++++
target/mips/translate_init.c.inc | 34 ------------------------------
3 files changed, 38 insertions(+), 34 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 3bd41239b1d..7813eb224c9 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -201,6 +201,8 @@ void mips_tcg_init(void);
void cpu_state_reset(CPUMIPSState *s);
void cpu_mips_realize_env(CPUMIPSState *env);
+void msa_reset(CPUMIPSState *env);
+
/* cp0_timer.c */
uint32_t cpu_mips_get_count(CPUMIPSState *env);
void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
diff --git a/target/mips/mod-msa_helper.c b/target/mips/mod-msa_helper.c
index b89b4c44902..f0d728c03f0 100644
--- a/target/mips/mod-msa_helper.c
+++ b/target/mips/mod-msa_helper.c
@@ -8201,3 +8201,39 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t
df, uint32_t wd,
msa_move_v(pwd, pwx);
}
+
+void msa_reset(CPUMIPSState *env)
+{
+ if (!ase_msa_available(env)) {
+ return;
+ }
+
+#ifdef CONFIG_USER_ONLY
+ /* MSA access enabled */
+ env->CP0_Config5 |= 1 << CP0C5_MSAEn;
+ env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
+#endif
+
+ /*
+ * MSA CSR:
+ * - non-signaling floating point exception mode off (NX bit is 0)
+ * - Cause, Enables, and Flags are all 0
+ * - round to nearest / ties to even (RM bits are 0)
+ */
+ env->active_tc.msacsr = 0;
+
+ restore_msa_fp_status(env);
+
+ /* tininess detected after rounding.*/
+ set_float_detect_tininess(float_tininess_after_rounding,
+ &env->active_tc.msa_fp_status);
+
+ /* clear float_status exception flags */
+ set_float_exception_flags(0, &env->active_tc.msa_fp_status);
+
+ /* clear float_status nan mode */
+ set_default_nan_mode(0, &env->active_tc.msa_fp_status);
+
+ /* set proper signanling bit meaning ("1" means "quiet") */
+ set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
+}
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index f6752d00afe..4856f4c5a4a 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -1021,37 +1021,3 @@ static void mvp_init(CPUMIPSState *env)
(0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
(0x1 << CP0MVPC1_PCP1);
}
-
-static void msa_reset(CPUMIPSState *env)
-{
- if (!ase_msa_available(env)) {
- return;
- }
-
-#ifdef CONFIG_USER_ONLY
- /* MSA access enabled */
- env->CP0_Config5 |= 1 << CP0C5_MSAEn;
- env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
-#endif
-
- /* MSA CSR:
- - non-signaling floating point exception mode off (NX bit is 0)
- - Cause, Enables, and Flags are all 0
- - round to nearest / ties to even (RM bits are 0) */
- env->active_tc.msacsr = 0;
-
- restore_msa_fp_status(env);
-
- /* tininess detected after rounding.*/
- set_float_detect_tininess(float_tininess_after_rounding,
- &env->active_tc.msa_fp_status);
-
- /* clear float_status exception flags */
- set_float_exception_flags(0, &env->active_tc.msa_fp_status);
-
- /* clear float_status nan mode */
- set_default_nan_mode(0, &env->active_tc.msa_fp_status);
-
- /* set proper signanling bit meaning ("1" means "quiet") */
- set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
-}
--
2.26.2
- [PATCH 01/17] target/mips: Introduce ase_msa_available() helper, (continued)
- [PATCH 01/17] target/mips: Introduce ase_msa_available() helper, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 02/17] target/mips: Simplify msa_reset(), Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 03/17] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 04/17] target/mips: Simplify MSA TCG logic, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 05/17] target/mips: Remove now unused ASE_MSA definition, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 06/17] target/mips: Alias MSA vector registers on FPU scalar registers, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 07/17] target/mips: Extract msa_translate_init() from mips_tcg_init(), Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 08/17] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 09/17] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ(), Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 10/17] target/mips: Rename msa_helper.c as mod-msa_helper.c, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 11/17] target/mips: Move msa_reset() to mod-msa_helper.c,
Philippe Mathieu-Daudé <=
- [PATCH 12/17] target/mips: Extract MSA helpers from op_helper.c, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 14/17] target/mips: Declare gen_msa/_branch() in 'translate.h', Philippe Mathieu-Daudé, 2020/12/07
[PATCH 16/17] target/mips: Introduce decode tree bindings for MSA opcodes, Philippe Mathieu-Daudé, 2020/12/07