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[PULL 18/36] target/arm: Refactor M-profile VMSR/VMRS handling
From: |
Peter Maydell |
Subject: |
[PULL 18/36] target/arm: Refactor M-profile VMSR/VMRS handling |
Date: |
Thu, 10 Dec 2020 11:47:38 +0000 |
Currently M-profile borrows the A-profile code for VMSR and VMRS
(access to the FP system registers), because all it needs to support
is the FPSCR. In v8.1M things become significantly more complicated
in two ways:
* there are several new FP system registers; some have side effects
on read, and one (FPCXT_NS) needs to avoid the usual
vfp_access_check() and the "only if FPU implemented" check
* all sysregs are now accessible both by VMRS/VMSR (which
reads/writes a general purpose register) and also by VLDR/VSTR
(which reads/writes them directly to memory)
Refactor the structure of how we handle VMSR/VMRS to cope with this:
* keep the M-profile code entirely separate from the A-profile code
* abstract out the "read or write the general purpose register" part
of the code into a loadfn or storefn function pointer, so we can
reuse it for VLDR/VSTR.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-8-peter.maydell@linaro.org
---
target/arm/cpu.h | 3 +
target/arm/translate-vfp.c.inc | 182 ++++++++++++++++++++++++++++++---
2 files changed, 171 insertions(+), 14 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 11400a9d248..ad8b80c667d 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1569,6 +1569,9 @@ enum arm_cpu_mode {
#define ARM_VFP_FPINST 9
#define ARM_VFP_FPINST2 10
+/* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
+#define QEMU_VFP_FPSCR_NZCV 0xffff
+
/* iwMMXt coprocessor control registers. */
#define ARM_IWMMXT_wCID 0
#define ARM_IWMMXT_wCon 1
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index e100182a32c..7a0cbca6640 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -607,27 +607,181 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
return true;
}
+/*
+ * M-profile provides two different sets of instructions that can
+ * access floating point system registers: VMSR/VMRS (which move
+ * to/from a general purpose register) and VLDR/VSTR sysreg (which
+ * move directly to/from memory). In some cases there are also side
+ * effects which must happen after any write to memory (which could
+ * cause an exception). So we implement the common logic for the
+ * sysreg access in gen_M_fp_sysreg_write() and gen_M_fp_sysreg_read(),
+ * which take pointers to callback functions which will perform the
+ * actual "read/write general purpose register" and "read/write
+ * memory" operations.
+ */
+
+/*
+ * Emit code to store the sysreg to its final destination; frees the
+ * TCG temp 'value' it is passed.
+ */
+typedef void fp_sysreg_storefn(DisasContext *s, void *opaque, TCGv_i32 value);
+/*
+ * Emit code to load the value to be copied to the sysreg; returns
+ * a new TCG temporary
+ */
+typedef TCGv_i32 fp_sysreg_loadfn(DisasContext *s, void *opaque);
+
+/* Common decode/access checks for fp sysreg read/write */
+typedef enum FPSysRegCheckResult {
+ FPSysRegCheckFailed, /* caller should return false */
+ FPSysRegCheckDone, /* caller should return true */
+ FPSysRegCheckContinue, /* caller should continue generating code */
+} FPSysRegCheckResult;
+
+static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
+{
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return FPSysRegCheckFailed;
+ }
+
+ switch (regno) {
+ case ARM_VFP_FPSCR:
+ case QEMU_VFP_FPSCR_NZCV:
+ break;
+ default:
+ return FPSysRegCheckFailed;
+ }
+
+ if (!vfp_access_check(s)) {
+ return FPSysRegCheckDone;
+ }
+
+ return FPSysRegCheckContinue;
+}
+
+static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
+
+ fp_sysreg_loadfn *loadfn,
+ void *opaque)
+{
+ /* Do a write to an M-profile floating point system register */
+ TCGv_i32 tmp;
+
+ switch (fp_sysreg_checks(s, regno)) {
+ case FPSysRegCheckFailed:
+ return false;
+ case FPSysRegCheckDone:
+ return true;
+ case FPSysRegCheckContinue:
+ break;
+ }
+
+ switch (regno) {
+ case ARM_VFP_FPSCR:
+ tmp = loadfn(s, opaque);
+ gen_helper_vfp_set_fpscr(cpu_env, tmp);
+ tcg_temp_free_i32(tmp);
+ gen_lookup_tb(s);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return true;
+}
+
+static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
+ fp_sysreg_storefn *storefn,
+ void *opaque)
+{
+ /* Do a read from an M-profile floating point system register */
+ TCGv_i32 tmp;
+
+ switch (fp_sysreg_checks(s, regno)) {
+ case FPSysRegCheckFailed:
+ return false;
+ case FPSysRegCheckDone:
+ return true;
+ case FPSysRegCheckContinue:
+ break;
+ }
+
+ switch (regno) {
+ case ARM_VFP_FPSCR:
+ tmp = tcg_temp_new_i32();
+ gen_helper_vfp_get_fpscr(tmp, cpu_env);
+ storefn(s, opaque, tmp);
+ break;
+ case QEMU_VFP_FPSCR_NZCV:
+ /*
+ * Read just NZCV; this is a special case to avoid the
+ * helper call for the "VMRS to CPSR.NZCV" insn.
+ */
+ tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
+ tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
+ storefn(s, opaque, tmp);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return true;
+}
+
+static void fp_sysreg_to_gpr(DisasContext *s, void *opaque, TCGv_i32 value)
+{
+ arg_VMSR_VMRS *a = opaque;
+
+ if (a->rt == 15) {
+ /* Set the 4 flag bits in the CPSR */
+ gen_set_nzcv(value);
+ tcg_temp_free_i32(value);
+ } else {
+ store_reg(s, a->rt, value);
+ }
+}
+
+static TCGv_i32 gpr_to_fp_sysreg(DisasContext *s, void *opaque)
+{
+ arg_VMSR_VMRS *a = opaque;
+
+ return load_reg(s, a->rt);
+}
+
+static bool gen_M_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
+{
+ /*
+ * Accesses to R15 are UNPREDICTABLE; we choose to undef.
+ * FPSCR -> r15 is a special case which writes to the PSR flags;
+ * set a->reg to a special value to tell gen_M_fp_sysreg_read()
+ * we only care about the top 4 bits of FPSCR there.
+ */
+ if (a->rt == 15) {
+ if (a->l && a->reg == ARM_VFP_FPSCR) {
+ a->reg = QEMU_VFP_FPSCR_NZCV;
+ } else {
+ return false;
+ }
+ }
+
+ if (a->l) {
+ /* VMRS, move FP system register to gp register */
+ return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_gpr, a);
+ } else {
+ /* VMSR, move gp register to FP system register */
+ return gen_M_fp_sysreg_write(s, a->reg, gpr_to_fp_sysreg, a);
+ }
+}
+
static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
{
TCGv_i32 tmp;
bool ignore_vfp_enabled = false;
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
- return false;
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
+ return gen_M_VMSR_VMRS(s, a);
}
- if (arm_dc_feature(s, ARM_FEATURE_M)) {
- /*
- * The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
- * Accesses to R15 are UNPREDICTABLE; we choose to undef.
- * (FPSCR -> r15 is a special case which writes to the PSR flags.)
- */
- if (a->reg != ARM_VFP_FPSCR) {
- return false;
- }
- if (a->rt == 15 && !a->l) {
- return false;
- }
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
}
switch (a->reg) {
--
2.20.1
- [PULL 10/36] i.MX6: Fix bad printf format specifiers, (continued)
- [PULL 10/36] i.MX6: Fix bad printf format specifiers, Peter Maydell, 2020/12/10
- [PULL 16/36] target/arm: Implement CLRM instruction, Peter Maydell, 2020/12/10
- [PULL 17/36] target/arm: Enforce M-profile VMRS/VMSR register restrictions, Peter Maydell, 2020/12/10
- [PULL 11/36] i.MX6ul: Fix bad printf format specifiers, Peter Maydell, 2020/12/10
- [PULL 13/36] target/arm: Implement v8.1M PXN extension, Peter Maydell, 2020/12/10
- [PULL 15/36] target/arm: Implement VSCCLRM insn, Peter Maydell, 2020/12/10
- [PULL 21/36] target/arm: Implement M-profile FPSCR_nzcvqc, Peter Maydell, 2020/12/10
- [PULL 25/36] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M, Peter Maydell, 2020/12/10
- [PULL 22/36] target/arm: Use new FPCR_NZCV_MASK constant, Peter Maydell, 2020/12/10
- [PULL 19/36] target/arm: Move general-use constant expanders up in translate.c, Peter Maydell, 2020/12/10
- [PULL 18/36] target/arm: Refactor M-profile VMSR/VMRS handling,
Peter Maydell <=
- [PULL 28/36] target/arm: Implement v8.1M REVIDR register, Peter Maydell, 2020/12/10
- [PULL 26/36] target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry, Peter Maydell, 2020/12/10
- [PULL 30/36] target/arm: Implement new v8.1M VLLDM and VLSTM encodings, Peter Maydell, 2020/12/10
- [PULL 34/36] target/arm: Implement M-profile "minimal RAS implementation", Peter Maydell, 2020/12/10
- [PULL 12/36] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault, Peter Maydell, 2020/12/10
- [PULL 20/36] target/arm: Implement VLDR/VSTR system register, Peter Maydell, 2020/12/10
- [PULL 31/36] hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit, Peter Maydell, 2020/12/10
- [PULL 36/36] hw/arm/armv7m: Correct typo in QOM object name, Peter Maydell, 2020/12/10
- [PULL 24/36] target/arm: Implement FPCXT_S fp system register, Peter Maydell, 2020/12/10
- [PULL 23/36] target/arm: Factor out preserve-fp-state from full_vfp_access_check(), Peter Maydell, 2020/12/10