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[PULL 24/36] target/arm: Implement FPCXT_S fp system register
From: |
Peter Maydell |
Subject: |
[PULL 24/36] target/arm: Implement FPCXT_S fp system register |
Date: |
Thu, 10 Dec 2020 11:47:44 +0000 |
Implement the new-in-v8.1M FPCXT_S floating point system register.
This is for saving and restoring the secure floating point context,
and it reads and writes bits [27:0] from the FPSCR and the
CONTROL.SFPA bit in bit [31].
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-14-peter.maydell@linaro.org
---
target/arm/translate-vfp.c.inc | 58 ++++++++++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index bb1c41413e7..808b4077054 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -662,6 +662,14 @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext
*s, int regno)
return false;
}
break;
+ case ARM_VFP_FPCXT_S:
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
+ return false;
+ }
+ if (!s->v8m_secure) {
+ return false;
+ }
+ break;
default:
return FPSysRegCheckFailed;
}
@@ -713,6 +721,26 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int
regno,
tcg_temp_free_i32(tmp);
break;
}
+ case ARM_VFP_FPCXT_S:
+ {
+ TCGv_i32 sfpa, control, fpscr;
+ /* Set FPSCR[27:0] and CONTROL.SFPA from value */
+ tmp = loadfn(s, opaque);
+ sfpa = tcg_temp_new_i32();
+ tcg_gen_shri_i32(sfpa, tmp, 31);
+ control = load_cpu_field(v7m.control[M_REG_S]);
+ tcg_gen_deposit_i32(control, control, sfpa,
+ R_V7M_CONTROL_SFPA_SHIFT, 1);
+ store_cpu_field(control, v7m.control[M_REG_S]);
+ fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
+ tcg_gen_andi_i32(fpscr, fpscr, FPCR_NZCV_MASK);
+ tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
+ tcg_gen_or_i32(fpscr, fpscr, tmp);
+ store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
+ tcg_temp_free_i32(tmp);
+ tcg_temp_free_i32(sfpa);
+ break;
+ }
default:
g_assert_not_reached();
}
@@ -756,6 +784,36 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int
regno,
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
storefn(s, opaque, tmp);
break;
+ case ARM_VFP_FPCXT_S:
+ {
+ TCGv_i32 control, sfpa, fpscr;
+ /* Bits [27:0] from FPSCR, bit [31] from CONTROL.SFPA */
+ tmp = tcg_temp_new_i32();
+ sfpa = tcg_temp_new_i32();
+ gen_helper_vfp_get_fpscr(tmp, cpu_env);
+ tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
+ control = load_cpu_field(v7m.control[M_REG_S]);
+ tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
+ tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);
+ tcg_gen_or_i32(tmp, tmp, sfpa);
+ tcg_temp_free_i32(sfpa);
+ /*
+ * Store result before updating FPSCR etc, in case
+ * it is a memory write which causes an exception.
+ */
+ storefn(s, opaque, tmp);
+ /*
+ * Now we must reset FPSCR from FPDSCR_NS, and clear
+ * CONTROL.SFPA; so we'll end the TB here.
+ */
+ tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK);
+ store_cpu_field(control, v7m.control[M_REG_S]);
+ fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
+ gen_helper_vfp_set_fpscr(cpu_env, fpscr);
+ tcg_temp_free_i32(fpscr);
+ gen_lookup_tb(s);
+ break;
+ }
default:
g_assert_not_reached();
}
--
2.20.1
- [PULL 19/36] target/arm: Move general-use constant expanders up in translate.c, (continued)
- [PULL 19/36] target/arm: Move general-use constant expanders up in translate.c, Peter Maydell, 2020/12/10
- [PULL 18/36] target/arm: Refactor M-profile VMSR/VMRS handling, Peter Maydell, 2020/12/10
- [PULL 28/36] target/arm: Implement v8.1M REVIDR register, Peter Maydell, 2020/12/10
- [PULL 26/36] target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry, Peter Maydell, 2020/12/10
- [PULL 30/36] target/arm: Implement new v8.1M VLLDM and VLSTM encodings, Peter Maydell, 2020/12/10
- [PULL 34/36] target/arm: Implement M-profile "minimal RAS implementation", Peter Maydell, 2020/12/10
- [PULL 12/36] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault, Peter Maydell, 2020/12/10
- [PULL 20/36] target/arm: Implement VLDR/VSTR system register, Peter Maydell, 2020/12/10
- [PULL 31/36] hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit, Peter Maydell, 2020/12/10
- [PULL 36/36] hw/arm/armv7m: Correct typo in QOM object name, Peter Maydell, 2020/12/10
- [PULL 24/36] target/arm: Implement FPCXT_S fp system register,
Peter Maydell <=
- [PULL 23/36] target/arm: Factor out preserve-fp-state from full_vfp_access_check(), Peter Maydell, 2020/12/10
- [PULL 27/36] target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures, Peter Maydell, 2020/12/10
- [PULL 29/36] target/arm: Implement new v8.1M NOCP check for exception return, Peter Maydell, 2020/12/10
- [PULL 32/36] target/arm: Implement CCR_S.TRD behaviour for SG insns, Peter Maydell, 2020/12/10
- [PULL 35/36] hw/intc/armv7m_nvic: Implement read/write for RAS register block, Peter Maydell, 2020/12/10
- [PULL 33/36] hw/intc/armv7m_nvic: Fix "return from inactive handler" check, Peter Maydell, 2020/12/10
- Re: [PULL 00/36] target-arm queue, Peter Maydell, 2020/12/10