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Re: [PULL 00/36] target-arm queue
From: |
Peter Maydell |
Subject: |
Re: [PULL 00/36] target-arm queue |
Date: |
Thu, 10 Dec 2020 12:51:36 +0000 |
On Thu, 10 Dec 2020 at 11:47, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> First pullreq for 6.0: mostly my v8.1M work, plus some other
> bits and pieces. (I still have a lot of stuff in my to-review
> folder, which I may or may not get to before the Christmas break...)
>
> thanks
> -- PMM
>
> The following changes since commit 5e7b204dbfae9a562fc73684986f936b97f63877:
>
> Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
> (2020-12-09 20:08:54 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20201210
>
> for you to fetch changes up to 71f916be1c7e9ede0e37d9cabc781b5a9e8638ff:
>
> hw/arm/armv7m: Correct typo in QOM object name (2020-12-10 11:44:56 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * hw/arm/smmuv3: Fix up L1STD_SPAN decoding
> * xlnx-zynqmp: Support Xilinx ZynqMP CAN controllers
> * sbsa-ref: allow to use Cortex-A53/57/72 cpus
> * Various minor code cleanups
> * hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
> * Implement more pieces of ARMv8.1M support
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.
-- PMM
- [PULL 20/36] target/arm: Implement VLDR/VSTR system register, (continued)
- [PULL 20/36] target/arm: Implement VLDR/VSTR system register, Peter Maydell, 2020/12/10
- [PULL 31/36] hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit, Peter Maydell, 2020/12/10
- [PULL 36/36] hw/arm/armv7m: Correct typo in QOM object name, Peter Maydell, 2020/12/10
- [PULL 24/36] target/arm: Implement FPCXT_S fp system register, Peter Maydell, 2020/12/10
- [PULL 23/36] target/arm: Factor out preserve-fp-state from full_vfp_access_check(), Peter Maydell, 2020/12/10
- [PULL 27/36] target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures, Peter Maydell, 2020/12/10
- [PULL 29/36] target/arm: Implement new v8.1M NOCP check for exception return, Peter Maydell, 2020/12/10
- [PULL 32/36] target/arm: Implement CCR_S.TRD behaviour for SG insns, Peter Maydell, 2020/12/10
- [PULL 35/36] hw/intc/armv7m_nvic: Implement read/write for RAS register block, Peter Maydell, 2020/12/10
- [PULL 33/36] hw/intc/armv7m_nvic: Fix "return from inactive handler" check, Peter Maydell, 2020/12/10
- Re: [PULL 00/36] target-arm queue,
Peter Maydell <=