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[PULL 11/26] target/mips: Rename cpu_supports_FEAT() as cpu_type_support
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 11/26] target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT() |
Date: |
Sun, 13 Dec 2020 21:19:31 +0100 |
As cpu_supports_isa() / cpu_supports_cps_smp() take a 'cpu_type'
name argument, rename them cpu_type_supports_FEAT().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201207215257.4004222-2-f4bug@amsat.org>
---
target/mips/cpu.h | 4 ++--
hw/mips/boston.c | 4 ++--
hw/mips/malta.c | 4 ++--
target/mips/translate.c | 4 ++--
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 23f8c6f96cd..9c65c87bf99 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1286,8 +1286,8 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo,
void *puc);
#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
-bool cpu_supports_cps_smp(const char *cpu_type);
-bool cpu_supports_isa(const char *cpu_type, uint64_t isa);
+bool cpu_type_supports_cps_smp(const char *cpu_type);
+bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa);
void cpu_set_exception_base(int vp_index, target_ulong address);
/* mips_int.c */
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 3d40867dc4c..16467ea4752 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -459,12 +459,12 @@ static void boston_mach_init(MachineState *machine)
s = BOSTON(dev);
s->mach = machine;
- if (!cpu_supports_cps_smp(machine->cpu_type)) {
+ if (!cpu_type_supports_cps_smp(machine->cpu_type)) {
error_report("Boston requires CPUs which support CPS");
exit(1);
}
- is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64);
+ is_64b = cpu_type_supports_isa(machine->cpu_type, ISA_MIPS64);
object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS);
object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type,
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 5c11eecec11..4651a1055c9 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -1205,7 +1205,7 @@ static void create_cps(MachineState *ms, MaltaState *s,
static void mips_create_cpu(MachineState *ms, MaltaState *s,
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
- if ((ms->smp.cpus > 1) && cpu_supports_cps_smp(ms->cpu_type)) {
+ if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) {
create_cps(ms, s, cbus_irq, i8259_irq);
} else {
create_cpu_without_cps(ms, s, cbus_irq, i8259_irq);
@@ -1309,7 +1309,7 @@ void mips_malta_init(MachineState *machine)
loaderparams.initrd_filename = initrd_filename;
kernel_entry = load_kernel();
- if (!cpu_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) {
+ if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) {
write_bootloader(memory_region_get_ram_ptr(bios),
bootloader_run_addr, kernel_entry);
} else {
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c64a1bc42e1..b8ed16bb779 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31770,13 +31770,13 @@ void cpu_mips_realize_env(CPUMIPSState *env)
mvp_init(env, env->cpu_model);
}
-bool cpu_supports_cps_smp(const char *cpu_type)
+bool cpu_type_supports_cps_smp(const char *cpu_type)
{
const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
}
-bool cpu_supports_isa(const char *cpu_type, uint64_t isa)
+bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa)
{
const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
return (mcc->cpu_def->insn_flags & isa) != 0;
--
2.26.2
- [PULL 01/26] MAINTAINERS: address@hidden -> address@hidden, (continued)
- [PULL 01/26] MAINTAINERS: address@hidden -> address@hidden, Philippe Mathieu-Daudé, 2020/12/13
- [PULL 03/26] target/mips/kvm: Remove unused headers, Philippe Mathieu-Daudé, 2020/12/13
- [PULL 04/26] target/mips: Include "exec/memattrs.h" in 'internal.h', Philippe Mathieu-Daudé, 2020/12/13
- [PULL 02/26] target/mips/kvm: Assert unreachable code is not used, Philippe Mathieu-Daudé, 2020/12/13
- [PULL 05/26] target/mips: Replace magic values by CP0PM_MASK or TARGET_PAGE_BITS_MIN, Philippe Mathieu-Daudé, 2020/12/13
- [PULL 06/26] target/mips: Do not include CP0 helpers in user-mode emulation, Philippe Mathieu-Daudé, 2020/12/13
- [PULL 07/26] target/mips: Remove unused headers from cp0_helper.c, Philippe Mathieu-Daudé, 2020/12/13
- [PULL 08/26] target/mips: Also display exception names in user-mode, Philippe Mathieu-Daudé, 2020/12/13
- [PULL 09/26] target/mips: Allow executing MSA instructions on Loongson-3A4000, Philippe Mathieu-Daudé, 2020/12/13
- [PULL 10/26] target/mips: Explicit Release 6 MMU types, Philippe Mathieu-Daudé, 2020/12/13
- [PULL 11/26] target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT(),
Philippe Mathieu-Daudé <=
- [PULL 12/26] target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argument, Philippe Mathieu-Daudé, 2020/12/13
- [PULL 13/26] hw/mips: Move address translation helpers to target/mips/, Philippe Mathieu-Daudé, 2020/12/13
- [PULL 15/26] target/mips: Remove unused headers from op_helper.c, Philippe Mathieu-Daudé, 2020/12/13
- [PULL 14/26] target/mips: Remove unused headers from translate.c, Philippe Mathieu-Daudé, 2020/12/13
- [PULL 16/26] target/mips: Remove mips_def_t unused argument from mvp_init(), Philippe Mathieu-Daudé, 2020/12/13
- [PULL 17/26] target/mips: Introduce ase_mt_available() helper, Philippe Mathieu-Daudé, 2020/12/13
- [PULL 18/26] target/mips: Do not initialize MT registers if MT ASE absent, Philippe Mathieu-Daudé, 2020/12/13
- [PULL 19/26] hw/mips/malta: Do not initialize MT registers if MT ASE absent, Philippe Mathieu-Daudé, 2020/12/13
- [PULL 20/26] hw/mips/malta: Rewrite CP0_MVPConf0 access using deposit(), Philippe Mathieu-Daudé, 2020/12/13
- [PULL 21/26] target/mips: Extract cpu_supports*/cpu_set* translate.c, Philippe Mathieu-Daudé, 2020/12/13