Re: [PATCH v3 1/4] hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN

[Richard Henderson]

On 12/10/20 2:14 PM, Peter Maydell wrote:
> The CCR is a register most of whose bits are banked between security
> states but where BFHFNMIGN is not, and we keep it in the non-secure
> entry of the v7m.ccr[] array.  The logic which tries to handle this
> bit fails to implement the "RAZ/WI from Nonsecure if AIRCR.BFHFNMINS
> is zero" requirement; correct the omission.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> Changes since v2: get the "WI" bit right
> ---
>  hw/intc/armv7m_nvic.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~