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Re: [PULL 00/23] riscv-to-apply queue
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From: |
Peter Maydell |
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Subject: |
Re: [PULL 00/23] riscv-to-apply queue |
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Date: |
Fri, 18 Dec 2020 13:36:52 +0000 |
On Fri, 18 Dec 2020 at 06:01, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 75ee62ac606bfc9eb59310b9446df3434bf6e8c2:
>
> Merge remote-tracking branch
> 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2020-12-17
> 18:53:36 +0000)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201217-1
>
> for you to fetch changes up to d31e970a01e7399b9cd43ec0dc00c857d968987e:
>
> riscv/opentitan: Update the OpenTitan memory layout (2020-12-17 21:56:44
> -0800)
>
> ----------------------------------------------------------------
> A collection of RISC-V improvements:
> - Improve the sifive_u DTB generation
> - Add QSPI NOR flash to Microchip PFSoC
> - Fix a bug in the Hypervisor HLVX/HLV/HSV instructions
> - Fix some mstatus mask defines
> - Ibex PLIC improvements
> - OpenTitan memory layout update
> - Initial steps towards support for 32-bit CPUs on 64-bit builds
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.
-- PMM
- [PULL 15/23] target/riscv: fpu_helper: Match function defs in HELPER macros, (continued)
- [PULL 15/23] target/riscv: fpu_helper: Match function defs in HELPER macros, Alistair Francis, 2020/12/18
- [PULL 13/23] hw/riscv: spike: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 16/23] target/riscv: Add a riscv_cpu_is_32bit() helper function, Alistair Francis, 2020/12/18
- [PULL 18/23] target/riscv: cpu: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 17/23] target/riscv: Specify the XLEN for CPUs, Alistair Francis, 2020/12/18
- [PULL 20/23] target/riscv: csr: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 19/23] target/riscv: cpu_helper: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 21/23] target/riscv: cpu: Set XLEN independently from target, Alistair Francis, 2020/12/18
- [PULL 22/23] hw/riscv: Use the CPU to determine if 32-bit, Alistair Francis, 2020/12/18
- [PULL 23/23] riscv/opentitan: Update the OpenTitan memory layout, Alistair Francis, 2020/12/18
- Re: [PULL 00/23] riscv-to-apply queue,
Peter Maydell <=