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[PATCH 03/15] tcg/arm: Implement tcg_out_mov for vector types
From: |
Richard Henderson |
Subject: |
[PATCH 03/15] tcg/arm: Implement tcg_out_mov for vector types |
Date: |
Thu, 24 Dec 2020 14:45:02 -0800 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.c.inc | 50 +++++++++++++++++++++++++++++++++++-----
1 file changed, 44 insertions(+), 6 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 7122d5f390..acc8f2c44a 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -178,6 +178,7 @@ typedef enum {
INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */
INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */
+ INSN_VMOV = 0xf2200110, /* VMOV (register) */
} ARMInsn;
#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
@@ -1086,6 +1087,25 @@ static uint32_t encode_vd(TCGReg rd)
return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13);
}
+static uint32_t encode_vn(TCGReg rn)
+{
+ tcg_debug_assert(rn >= TCG_REG_Q0);
+ return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17);
+}
+
+static uint32_t encode_vm(TCGReg rm)
+{
+ tcg_debug_assert(rm >= TCG_REG_Q0);
+ return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1);
+}
+
+static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
+ TCGReg d, TCGReg n, TCGReg m)
+{
+ tcg_out32(s, insn | (vece << 20) | (q << 6) |
+ encode_vd(d) | encode_vn(n) | encode_vm(m));
+}
+
static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
TCGReg rd, TCGReg rn, int offset)
{
@@ -2260,16 +2280,34 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType
type, TCGArg val,
return false;
}
-static inline bool tcg_out_mov(TCGContext *s, TCGType type,
- TCGReg ret, TCGReg arg)
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
- tcg_out_mov_reg(s, COND_AL, ret, arg);
- return true;
+ if (ret == arg) {
+ return true;
+ }
+ switch (type) {
+ case TCG_TYPE_I32:
+ if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) {
+ tcg_out_mov_reg(s, COND_AL, ret, arg);
+ return true;
+ }
+ return false;
+
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ tcg_out_vreg3(s, INSN_VMOV, type - TCG_TYPE_V64, 0, ret, arg, arg);
+ return true;
+
+ default:
+ g_assert_not_reached();
+ }
}
-static inline void tcg_out_movi(TCGContext *s, TCGType type,
- TCGReg ret, tcg_target_long arg)
+static void tcg_out_movi(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long arg)
{
+ tcg_debug_assert(type == TCG_TYPE_I32);
+ tcg_debug_assert(ret < TCG_REG_Q0);
tcg_out_movi32(s, COND_AL, ret, arg);
}
--
2.25.1
- [PATCH 00/15] tcg/arm: host neon support, Richard Henderson, 2020/12/24
- [PATCH 02/15] tcg/arm: Implement tcg_out_ld/st for vector types, Richard Henderson, 2020/12/24
- [PATCH 01/15] tcg/arm: Add host vector framework, Richard Henderson, 2020/12/24
- [PATCH 05/15] tcg: Change parameters for tcg_target_const_match, Richard Henderson, 2020/12/24
- [PATCH 04/15] tcg/arm: Implement tcg_out_dup*_vec, Richard Henderson, 2020/12/24
- [PATCH 06/15] tcg/arm: Implement minimal vector operations, Richard Henderson, 2020/12/24
- [PATCH 08/15] tcg/arm: Implement TCG_TARGET_HAS_shi_vec, Richard Henderson, 2020/12/24
- [PATCH 11/15] tcg/arm: Implement TCG_TARGET_HAS_minmax_vec, Richard Henderson, 2020/12/24
- [PATCH 13/15] tcg/arm: Implement TCG_TARGET_HAS_shv_vec, Richard Henderson, 2020/12/24
- [PATCH 03/15] tcg/arm: Implement tcg_out_mov for vector types,
Richard Henderson <=
- [PATCH 07/15] tcg/arm: Implement andc, orc, abs, neg, not vector operations, Richard Henderson, 2020/12/24
- [PATCH 09/15] tcg/arm: Implement TCG_TARGET_HAS_mul_vec, Richard Henderson, 2020/12/24
- [PATCH 10/15] tcg/arm: Implement TCG_TARGET_HAS_sat_vec, Richard Henderson, 2020/12/24
- [PATCH 14/15] tcg/arm: Implement TCG_TARGET_HAS_roti_vec, Richard Henderson, 2020/12/24
- [PATCH 15/15] tcg/arm: Implement TCG_TARGET_HAS_rotv_vec, Richard Henderson, 2020/12/24
- [PATCH 12/15] tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec, Richard Henderson, 2020/12/24