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[PATCH 09/15] tcg/arm: Implement TCG_TARGET_HAS_mul_vec
From: |
Richard Henderson |
Subject: |
[PATCH 09/15] tcg/arm: Implement TCG_TARGET_HAS_mul_vec |
Date: |
Thu, 24 Dec 2020 14:45:08 -0800 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.c.inc | 6 ++++++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 344b0d3199..8e5b304a5a 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -165,7 +165,7 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 0
-#define TCG_TARGET_HAS_mul_vec 0
+#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 0
#define TCG_TARGET_HAS_minmax_vec 0
#define TCG_TARGET_HAS_bitsel_vec 0
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index f5d10e262a..d11efc553a 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -186,6 +186,7 @@ typedef enum {
INSN_VORN = 0xf2300110,
INSN_VORR = 0xf2200110,
INSN_VSUB = 0xf3000800,
+ INSN_VMUL = 0xf2000910,
INSN_VABS = 0xf3b10300,
INSN_VMVN = 0xf3b00580,
@@ -2371,6 +2372,7 @@ static int tcg_target_op_def(TCGOpcode op)
return C_O1_I1(w, w);
case INDEX_op_dup2_vec:
case INDEX_op_add_vec:
+ case INDEX_op_mul_vec:
case INDEX_op_sub_vec:
case INDEX_op_xor_vec:
return C_O1_I2(w, w, w);
@@ -2735,6 +2737,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_add_vec:
tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
return;
+ case INDEX_op_mul_vec:
+ tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2);
+ return;
case INDEX_op_sub_vec:
tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
return;
@@ -2851,6 +2856,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
return 1;
case INDEX_op_abs_vec:
case INDEX_op_cmp_vec:
+ case INDEX_op_mul_vec:
case INDEX_op_neg_vec:
return vece < MO_64;
default:
--
2.25.1
- [PATCH 02/15] tcg/arm: Implement tcg_out_ld/st for vector types, (continued)
- [PATCH 02/15] tcg/arm: Implement tcg_out_ld/st for vector types, Richard Henderson, 2020/12/24
- [PATCH 01/15] tcg/arm: Add host vector framework, Richard Henderson, 2020/12/24
- [PATCH 05/15] tcg: Change parameters for tcg_target_const_match, Richard Henderson, 2020/12/24
- [PATCH 04/15] tcg/arm: Implement tcg_out_dup*_vec, Richard Henderson, 2020/12/24
- [PATCH 06/15] tcg/arm: Implement minimal vector operations, Richard Henderson, 2020/12/24
- [PATCH 08/15] tcg/arm: Implement TCG_TARGET_HAS_shi_vec, Richard Henderson, 2020/12/24
- [PATCH 11/15] tcg/arm: Implement TCG_TARGET_HAS_minmax_vec, Richard Henderson, 2020/12/24
- [PATCH 13/15] tcg/arm: Implement TCG_TARGET_HAS_shv_vec, Richard Henderson, 2020/12/24
- [PATCH 03/15] tcg/arm: Implement tcg_out_mov for vector types, Richard Henderson, 2020/12/24
- [PATCH 07/15] tcg/arm: Implement andc, orc, abs, neg, not vector operations, Richard Henderson, 2020/12/24
- [PATCH 09/15] tcg/arm: Implement TCG_TARGET_HAS_mul_vec,
Richard Henderson <=
- [PATCH 10/15] tcg/arm: Implement TCG_TARGET_HAS_sat_vec, Richard Henderson, 2020/12/24
- [PATCH 14/15] tcg/arm: Implement TCG_TARGET_HAS_roti_vec, Richard Henderson, 2020/12/24
- [PATCH 15/15] tcg/arm: Implement TCG_TARGET_HAS_rotv_vec, Richard Henderson, 2020/12/24
- [PATCH 12/15] tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec, Richard Henderson, 2020/12/24