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[PULL 04/49] target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU
From: |
Peter Maydell |
Subject: |
[PULL 04/49] target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU |
Date: |
Fri, 5 Mar 2021 17:14:30 +0000 |
From: Rebecca Cran <rebecca@nuviainc.com>
Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210216224543.16142-3-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu64.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index c255f1bcc39..f0a9e968c9c 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -674,6 +674,7 @@ static void aarch64_max_initfn(Object *obj)
t = cpu->isar.id_aa64pfr1;
t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
+ t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
/*
* Begin with full support for MTE. This will be downgraded to MTE=0
* during realize if the board provides no tag memory, much like
@@ -723,6 +724,10 @@ static void aarch64_max_initfn(Object *obj)
u = FIELD_DP32(u, ID_PFR0, DIT, 1);
cpu->isar.id_pfr0 = u;
+ u = cpu->isar.id_pfr2;
+ u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
+ cpu->isar.id_pfr2 = u;
+
u = cpu->isar.id_mmfr3;
u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
cpu->isar.id_mmfr3 = u;
--
2.20.1
- [PULL 00/49] target-arm queue, Peter Maydell, 2021/03/05
- [PULL 01/49] sbsa-ref: remove cortex-a53 from list of supported cpus, Peter Maydell, 2021/03/05
- [PULL 04/49] target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU,
Peter Maydell <=
- [PULL 02/49] sbsa-ref: add 'max' to list of allowed cpus, Peter Maydell, 2021/03/05
- [PULL 03/49] target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe, Peter Maydell, 2021/03/05
- [PULL 08/49] tests/qtests: Add npcm7xx emc model test, Peter Maydell, 2021/03/05
- [PULL 12/49] virtio-mmio: improve virtio-mmio get_dev_path alog, Peter Maydell, 2021/03/05
- [PULL 05/49] target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU, Peter Maydell, 2021/03/05
- [PULL 07/49] hw/arm: Add npcm7xx emc model, Peter Maydell, 2021/03/05
- [PULL 11/49] hw/i2c/npcm7xx_smbus: Simplify npcm7xx_smbus_init(), Peter Maydell, 2021/03/05
- [PULL 06/49] hw/net: Add npcm7xx emc model, Peter Maydell, 2021/03/05
- [PULL 10/49] target/arm: Speed up aarch64 TBL/TBX, Peter Maydell, 2021/03/05
- [PULL 09/49] hw/arm/xlnx-zynqmp: Remove obsolete 'has_rpu' property, Peter Maydell, 2021/03/05