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[PULL 15/54] hw/misc/iotkit-sysctl: Handle INITSVTOR* for SSE-300
From: |
Peter Maydell |
Subject: |
[PULL 15/54] hw/misc/iotkit-sysctl: Handle INITSVTOR* for SSE-300 |
Date: |
Mon, 8 Mar 2021 17:32:05 +0000 |
The SSE-300 has only one CPU and so no INITSVTOR1. It does
have INITSVTOR0, but unlike the SSE-200 this register now
has a LOCK bit which can be set to 1 to prevent any further
writes to the register. Implement these differences.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-16-peter.maydell@linaro.org
---
hw/misc/iotkit-sysctl.c | 27 +++++++++++++++++++++++++--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
index 54004bebcbf..511ede089c2 100644
--- a/hw/misc/iotkit-sysctl.c
+++ b/hw/misc/iotkit-sysctl.c
@@ -45,6 +45,8 @@ REG32(SWRESET, 0x108)
FIELD(SWRESET, SWRESETREQ, 9, 1)
REG32(GRETREG, 0x10c)
REG32(INITSVTOR0, 0x110)
+ FIELD(INITSVTOR0, LOCK, 0, 1)
+ FIELD(INITSVTOR0, VTOR, 7, 25)
REG32(INITSVTOR1, 0x114)
REG32(CPUWAIT, 0x118)
REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */
@@ -167,6 +169,8 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr
offset,
case ARMSSE_SSE200:
r = s->initsvtor1;
break;
+ case ARMSSE_SSE300:
+ goto bad_offset;
default:
g_assert_not_reached();
}
@@ -358,8 +362,25 @@ static void iotkit_sysctl_write(void *opaque, hwaddr
offset,
s->gretreg = value;
break;
case A_INITSVTOR0:
- s->initsvtor0 = value;
- set_init_vtor(0, s->initsvtor0);
+ switch (s->sse_version) {
+ case ARMSSE_SSE300:
+ /* SSE300 has a LOCK bit which prevents further writes when set */
+ if (s->initsvtor0 & R_INITSVTOR0_LOCK_MASK) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "IoTKit INITSVTOR0 write when register
locked\n");
+ break;
+ }
+ s->initsvtor0 = value;
+ set_init_vtor(0, s->initsvtor0 & R_INITSVTOR0_VTOR_MASK);
+ break;
+ case ARMSSE_IOTKIT:
+ case ARMSSE_SSE200:
+ s->initsvtor0 = value;
+ set_init_vtor(0, s->initsvtor0);
+ break;
+ default:
+ g_assert_not_reached();
+ }
break;
case A_CPUWAIT:
switch (s->sse_version) {
@@ -464,6 +485,8 @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
s->initsvtor1 = value;
set_init_vtor(1, s->initsvtor1);
break;
+ case ARMSSE_SSE300:
+ goto bad_offset;
default:
g_assert_not_reached();
}
--
2.20.1
- [PULL 00/54] target-arm queue, Peter Maydell, 2021/03/08
- [PULL 02/54] clock: Add ClockPreUpdate callback event type, Peter Maydell, 2021/03/08
- [PULL 03/54] clock: Add clock_ns_to_ticks() function, Peter Maydell, 2021/03/08
- [PULL 04/54] hw/timer/npcm7xx_timer: Use new clock_ns_to_ticks(), Peter Maydell, 2021/03/08
- [PULL 01/54] clock: Add ClockEvent parameter to callbacks, Peter Maydell, 2021/03/08
- [PULL 05/54] hw/arm/armsse: Introduce SSE subsystem version property, Peter Maydell, 2021/03/08
- [PULL 06/54] hw/misc/iotkit-sysctl: Remove is_sse200 flag, Peter Maydell, 2021/03/08
- [PULL 10/54] hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDR, Peter Maydell, 2021/03/08
- [PULL 15/54] hw/misc/iotkit-sysctl: Handle INITSVTOR* for SSE-300,
Peter Maydell <=
- [PULL 08/54] hw/misc/iotkit-sysinfo.c: Implement SSE-300 PID register values, Peter Maydell, 2021/03/08
- [PULL 11/54] hw/timer/sse-counter: Model the SSE Subsystem System Counter, Peter Maydell, 2021/03/08
- [PULL 07/54] hw/misc/iotkit-secctl.c: Implement SSE-300 PID register values, Peter Maydell, 2021/03/08
- [PULL 09/54] hw/arm/armsse.c: Use correct SYS_CONFIG0 register value for SSE-300, Peter Maydell, 2021/03/08
- [PULL 14/54] hw/misc/iotkit-sysctl: Handle CPU_WAIT, NMI_ENABLE for SSE-300, Peter Maydell, 2021/03/08
- [PULL 16/54] hw/misc/iotkit-sysctl: Implement dummy version of SSE-300 PWRCTRL register, Peter Maydell, 2021/03/08
- [PULL 12/54] hw/timer/sse-timer: Model the SSE Subsystem System Timer, Peter Maydell, 2021/03/08
- [PULL 13/54] hw/misc/iotkit-sysctl: Add SSE-300 cases which match SSE-200 behaviour, Peter Maydell, 2021/03/08
- [PULL 17/54] hw/misc/iotkit-sysctl: Handle SSE-300 changes to PDCM_PD_*_SENSE registers, Peter Maydell, 2021/03/08
- [PULL 21/54] hw/arm/armsse: Use an array for apb_ppc fields in the state structure, Peter Maydell, 2021/03/08