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[PULL 09/54] hw/arm/armsse.c: Use correct SYS_CONFIG0 register value for
From: |
Peter Maydell |
Subject: |
[PULL 09/54] hw/arm/armsse.c: Use correct SYS_CONFIG0 register value for SSE-300 |
Date: |
Mon, 8 Mar 2021 17:31:59 +0000 |
In the SSE-300, the format of the SYS_CONFIG0 register has changed again;
pass through the correct value to the SYSINFO register block device.
We drop the old SysConfigFormat enum, which was implemented in the
hope that different flavours of SSE would share the same format;
since they all seem to be different and we now have an sse_version
enum to key off, just use that.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-10-peter.maydell@linaro.org
---
hw/arm/armsse.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index 67fa4ffe34a..113a783a46a 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -24,12 +24,6 @@
#include "hw/irq.h"
#include "hw/qdev-clock.h"
-/* Format of the System Information block SYS_CONFIG register */
-typedef enum SysConfigFormat {
- IoTKitFormat,
- SSE200Format,
-} SysConfigFormat;
-
struct ARMSSEInfo {
const char *name;
uint32_t sse_version;
@@ -37,7 +31,6 @@ struct ARMSSEInfo {
int num_cpus;
uint32_t sys_version;
uint32_t cpuwait_rst;
- SysConfigFormat sys_config_format;
bool has_mhus;
bool has_ppus;
bool has_cachectrl;
@@ -78,7 +71,6 @@ static const ARMSSEInfo armsse_variants[] = {
.num_cpus = 1,
.sys_version = 0x41743,
.cpuwait_rst = 0,
- .sys_config_format = IoTKitFormat,
.has_mhus = false,
.has_ppus = false,
.has_cachectrl = false,
@@ -93,7 +85,6 @@ static const ARMSSEInfo armsse_variants[] = {
.num_cpus = 2,
.sys_version = 0x22041743,
.cpuwait_rst = 2,
- .sys_config_format = SSE200Format,
.has_mhus = true,
.has_ppus = true,
.has_cachectrl = true,
@@ -108,13 +99,13 @@ static uint32_t armsse_sys_config_value(ARMSSE *s, const
ARMSSEInfo *info)
/* Return the SYS_CONFIG value for this SSE */
uint32_t sys_config;
- switch (info->sys_config_format) {
- case IoTKitFormat:
+ switch (info->sse_version) {
+ case ARMSSE_IOTKIT:
sys_config = 0;
sys_config = deposit32(sys_config, 0, 4, info->sram_banks);
sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12);
break;
- case SSE200Format:
+ case ARMSSE_SSE200:
sys_config = 0;
sys_config = deposit32(sys_config, 0, 4, info->sram_banks);
sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width);
@@ -125,6 +116,12 @@ static uint32_t armsse_sys_config_value(ARMSSE *s, const
ARMSSEInfo *info)
sys_config = deposit32(sys_config, 28, 4, 2);
}
break;
+ case ARMSSE_SSE300:
+ sys_config = 0;
+ sys_config = deposit32(sys_config, 0, 4, info->sram_banks);
+ sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width);
+ sys_config = deposit32(sys_config, 16, 3, 3); /* CPU0 = Cortex-M55 */
+ break;
default:
g_assert_not_reached();
}
--
2.20.1
- [PULL 03/54] clock: Add clock_ns_to_ticks() function, (continued)
- [PULL 03/54] clock: Add clock_ns_to_ticks() function, Peter Maydell, 2021/03/08
- [PULL 04/54] hw/timer/npcm7xx_timer: Use new clock_ns_to_ticks(), Peter Maydell, 2021/03/08
- [PULL 01/54] clock: Add ClockEvent parameter to callbacks, Peter Maydell, 2021/03/08
- [PULL 05/54] hw/arm/armsse: Introduce SSE subsystem version property, Peter Maydell, 2021/03/08
- [PULL 06/54] hw/misc/iotkit-sysctl: Remove is_sse200 flag, Peter Maydell, 2021/03/08
- [PULL 10/54] hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDR, Peter Maydell, 2021/03/08
- [PULL 15/54] hw/misc/iotkit-sysctl: Handle INITSVTOR* for SSE-300, Peter Maydell, 2021/03/08
- [PULL 08/54] hw/misc/iotkit-sysinfo.c: Implement SSE-300 PID register values, Peter Maydell, 2021/03/08
- [PULL 11/54] hw/timer/sse-counter: Model the SSE Subsystem System Counter, Peter Maydell, 2021/03/08
- [PULL 07/54] hw/misc/iotkit-secctl.c: Implement SSE-300 PID register values, Peter Maydell, 2021/03/08
- [PULL 09/54] hw/arm/armsse.c: Use correct SYS_CONFIG0 register value for SSE-300,
Peter Maydell <=
- [PULL 14/54] hw/misc/iotkit-sysctl: Handle CPU_WAIT, NMI_ENABLE for SSE-300, Peter Maydell, 2021/03/08
- [PULL 16/54] hw/misc/iotkit-sysctl: Implement dummy version of SSE-300 PWRCTRL register, Peter Maydell, 2021/03/08
- [PULL 12/54] hw/timer/sse-timer: Model the SSE Subsystem System Timer, Peter Maydell, 2021/03/08
- [PULL 13/54] hw/misc/iotkit-sysctl: Add SSE-300 cases which match SSE-200 behaviour, Peter Maydell, 2021/03/08
- [PULL 17/54] hw/misc/iotkit-sysctl: Handle SSE-300 changes to PDCM_PD_*_SENSE registers, Peter Maydell, 2021/03/08
- [PULL 21/54] hw/arm/armsse: Use an array for apb_ppc fields in the state structure, Peter Maydell, 2021/03/08
- [PULL 20/54] hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU<N>_PWRCTRL register block, Peter Maydell, 2021/03/08
- [PULL 23/54] hw/arm/armsse: Add framework for data-driven device placement, Peter Maydell, 2021/03/08
- [PULL 25/54] hw/arm/armsse: Move watchdogs into data-driven framework, Peter Maydell, 2021/03/08
- [PULL 26/54] hw/arm/armsse: Move s32ktimer into data-driven framework, Peter Maydell, 2021/03/08