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[PULL 25/54] hw/arm/armsse: Move watchdogs into data-driven framework
From: |
Peter Maydell |
Subject: |
[PULL 25/54] hw/arm/armsse: Move watchdogs into data-driven framework |
Date: |
Mon, 8 Mar 2021 17:32:15 +0000 |
Move the CMSDK watchdog device handling into the data-driven device
placement framework. This is slightly more complicated because these
devices might wire their IRQs up to the NMI line, and because one of
them uses the slow 32KHz clock rather than the main clock.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-26-peter.maydell@linaro.org
---
include/hw/arm/armsse.h | 4 +-
hw/arm/armsse.c | 109 ++++++++++++++++++++++++----------------
2 files changed, 66 insertions(+), 47 deletions(-)
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index c1f4df295a4..3f8f3750577 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -171,9 +171,7 @@ struct ARMSSE {
CMSDKAPBDualTimer dualtimer;
- CMSDKAPBWatchdog s32kwatchdog;
- CMSDKAPBWatchdog nswatchdog;
- CMSDKAPBWatchdog swatchdog;
+ CMSDKAPBWatchdog cmsdk_watchdog[3];
IoTKitSysCtl sysctl;
IoTKitSysCtl sysinfo;
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index f8da7fb00f9..6540ffb919b 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -34,6 +34,13 @@
#define NO_IRQ -1
#define NO_PPC -1
+/*
+ * Special values for ARMSSEDeviceInfo::irq to indicate that this
+ * device uses one of the inputs to the OR gate that feeds into the
+ * CPU NMI input.
+ */
+#define NMI_0 10000
+#define NMI_1 10001
typedef struct ARMSSEDeviceInfo {
const char *name; /* name to use for the QOM object; NULL terminates list
*/
@@ -42,7 +49,8 @@ typedef struct ARMSSEDeviceInfo {
hwaddr addr;
int ppc; /* Index of APB PPC this device is wired up to, or NO_PPC */
int ppc_port; /* Port number of this device on the PPC */
- int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1 */
+ int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */
+ bool slowclk; /* true if device uses the slow 32KHz clock */
} ARMSSEDeviceInfo;
struct ARMSSEInfo {
@@ -114,6 +122,31 @@ static const ARMSSEDeviceInfo sse200_devices[] = {
.ppc_port = 2,
.irq = 5,
},
+ {
+ .name = "s32kwatchdog",
+ .type = TYPE_CMSDK_APB_WATCHDOG,
+ .index = 0,
+ .addr = 0x5002e000,
+ .ppc = NO_PPC,
+ .irq = NMI_0,
+ .slowclk = true,
+ },
+ {
+ .name = "nswatchdog",
+ .type = TYPE_CMSDK_APB_WATCHDOG,
+ .index = 1,
+ .addr = 0x40081000,
+ .ppc = NO_PPC,
+ .irq = 1,
+ },
+ {
+ .name = "swatchdog",
+ .type = TYPE_CMSDK_APB_WATCHDOG,
+ .index = 2,
+ .addr = 0x50081000,
+ .ppc = NO_PPC,
+ .irq = NMI_1,
+ },
{
.name = NULL,
}
@@ -359,6 +392,11 @@ static void armsse_init(Object *obj)
assert(devinfo->index == 0);
object_initialize_child(obj, devinfo->name, &s->dualtimer,
TYPE_CMSDK_APB_DUALTIMER);
+ } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) {
+ assert(devinfo->index < ARRAY_SIZE(s->cmsdk_watchdog));
+ object_initialize_child(obj, devinfo->name,
+ &s->cmsdk_watchdog[devinfo->index],
+ TYPE_CMSDK_APB_WATCHDOG);
} else {
g_assert_not_reached();
}
@@ -386,14 +424,9 @@ static void armsse_init(Object *obj)
object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ);
g_free(name);
}
+
object_initialize_child(obj, "s32ktimer", &s->s32ktimer,
TYPE_CMSDK_APB_TIMER);
- object_initialize_child(obj, "s32kwatchdog", &s->s32kwatchdog,
- TYPE_CMSDK_APB_WATCHDOG);
- object_initialize_child(obj, "nswatchdog", &s->nswatchdog,
- TYPE_CMSDK_APB_WATCHDOG);
- object_initialize_child(obj, "swatchdog", &s->swatchdog,
- TYPE_CMSDK_APB_WATCHDOG);
object_initialize_child(obj, "armsse-sysctl", &s->sysctl,
TYPE_IOTKIT_SYSCTL);
object_initialize_child(obj, "armsse-sysinfo", &s->sysinfo,
@@ -797,6 +830,17 @@ static void armsse_realize(DeviceState *dev, Error **errp)
qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0,
armsse_get_common_irq_in(s, 9));
+ /* This OR gate wires together outputs from the secure watchdogs to NMI */
+ if (!object_property_set_int(OBJECT(&s->nmi_orgate), "num-lines", 2,
+ errp)) {
+ return;
+ }
+ if (!qdev_realize(DEVICE(&s->nmi_orgate), NULL, errp)) {
+ return;
+ }
+ qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0,
+ qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI",
0));
+
/* Devices behind APB PPC0:
* 0x40000000: timer0
* 0x40001000: timer1
@@ -827,6 +871,15 @@ static void armsse_realize(DeviceState *dev, Error **errp)
return;
}
mr = sysbus_mmio_get_region(sbd, 0);
+ } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) {
+ sbd = SYS_BUS_DEVICE(&s->cmsdk_watchdog[devinfo->index]);
+
+ qdev_connect_clock_in(DEVICE(sbd), "WDOGCLK",
+ devinfo->slowclk ? s->s32kclk : s->mainclk);
+ if (!sysbus_realize(sbd, errp)) {
+ return;
+ }
+ mr = sysbus_mmio_get_region(sbd, 0);
} else {
g_assert_not_reached();
}
@@ -838,6 +891,11 @@ static void armsse_realize(DeviceState *dev, Error **errp)
case 0 ... NUM_SSE_IRQS - 1:
irq = armsse_get_common_irq_in(s, devinfo->irq);
break;
+ case NMI_0:
+ case NMI_1:
+ irq = qdev_get_gpio_in(DEVICE(&s->nmi_orgate),
+ devinfo->irq - NMI_0);
+ break;
default:
g_assert_not_reached();
}
@@ -1108,43 +1166,6 @@ static void armsse_realize(DeviceState *dev, Error
**errp)
}
}
- /* This OR gate wires together outputs from the secure watchdogs to NMI */
- if (!object_property_set_int(OBJECT(&s->nmi_orgate), "num-lines", 2,
- errp)) {
- return;
- }
- if (!qdev_realize(DEVICE(&s->nmi_orgate), NULL, errp)) {
- return;
- }
- qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0,
- qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI",
0));
-
- qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk);
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) {
- return;
- }
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32kwatchdog), 0,
- qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 0));
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 0x5002e000);
-
- /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */
-
- qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk);
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) {
- return;
- }
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->nswatchdog), 0,
- armsse_get_common_irq_in(s, 1));
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000);
-
- qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk);
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) {
- return;
- }
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->swatchdog), 0,
- qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 1));
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->swatchdog), 0, 0x50081000);
-
for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) {
Object *splitter = OBJECT(&s->ppc_irq_splitter[i]);
--
2.20.1
- [PULL 07/54] hw/misc/iotkit-secctl.c: Implement SSE-300 PID register values, (continued)
- [PULL 07/54] hw/misc/iotkit-secctl.c: Implement SSE-300 PID register values, Peter Maydell, 2021/03/08
- [PULL 09/54] hw/arm/armsse.c: Use correct SYS_CONFIG0 register value for SSE-300, Peter Maydell, 2021/03/08
- [PULL 14/54] hw/misc/iotkit-sysctl: Handle CPU_WAIT, NMI_ENABLE for SSE-300, Peter Maydell, 2021/03/08
- [PULL 16/54] hw/misc/iotkit-sysctl: Implement dummy version of SSE-300 PWRCTRL register, Peter Maydell, 2021/03/08
- [PULL 12/54] hw/timer/sse-timer: Model the SSE Subsystem System Timer, Peter Maydell, 2021/03/08
- [PULL 13/54] hw/misc/iotkit-sysctl: Add SSE-300 cases which match SSE-200 behaviour, Peter Maydell, 2021/03/08
- [PULL 17/54] hw/misc/iotkit-sysctl: Handle SSE-300 changes to PDCM_PD_*_SENSE registers, Peter Maydell, 2021/03/08
- [PULL 21/54] hw/arm/armsse: Use an array for apb_ppc fields in the state structure, Peter Maydell, 2021/03/08
- [PULL 20/54] hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU<N>_PWRCTRL register block, Peter Maydell, 2021/03/08
- [PULL 23/54] hw/arm/armsse: Add framework for data-driven device placement, Peter Maydell, 2021/03/08
- [PULL 25/54] hw/arm/armsse: Move watchdogs into data-driven framework,
Peter Maydell <=
- [PULL 26/54] hw/arm/armsse: Move s32ktimer into data-driven framework, Peter Maydell, 2021/03/08
- [PULL 30/54] hw/arm/armsse: Add missing SSE-200 SYS_PPU, Peter Maydell, 2021/03/08
- [PULL 22/54] hw/arm/armsse: Add a define for number of IRQs used by the SSE itself, Peter Maydell, 2021/03/08
- [PULL 32/54] hw/arm/armsse: Add support for SSE variants with a system counter, Peter Maydell, 2021/03/08
- [PULL 19/54] hw/arm/Kconfig: Move ARMSSE_CPUID and ARMSSE_MHU stanzas to hw/misc, Peter Maydell, 2021/03/08
- [PULL 18/54] hw/misc/iotkit-sysctl: Implement SSE-200 and SSE-300 PID register values, Peter Maydell, 2021/03/08
- [PULL 27/54] hw/arm/armsse: Move sysinfo register block into data-driven framework, Peter Maydell, 2021/03/08
- [PULL 28/54] hw/arm/armsse: Move sysctl register block into data-driven framework, Peter Maydell, 2021/03/08
- [PULL 31/54] hw/arm/armsse: Indirect irq_is_common[] through ARMSSEInfo, Peter Maydell, 2021/03/08
- [PULL 29/54] hw/arm/armsse: Move PPUs into data-driven framework, Peter Maydell, 2021/03/08