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[PULL 39/54] hw/misc/mps2-scc: Implement changes for AN547
From: |
Peter Maydell |
Subject: |
[PULL 39/54] hw/misc/mps2-scc: Implement changes for AN547 |
Date: |
Mon, 8 Mar 2021 17:32:29 +0000 |
Implement the minor changes required to the SCC block for AN547 images:
* CFG2 and CFG5 exist (like AN524)
* CFG3 is reserved (like AN524)
* CFG0 bit 1 is CPU_WAIT; we don't implement it, but note this
in the TODO comment
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-40-peter.maydell@linaro.org
---
hw/misc/mps2-scc.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
index 140a4b9ceba..c56aca86ad5 100644
--- a/hw/misc/mps2-scc.c
+++ b/hw/misc/mps2-scc.c
@@ -110,14 +110,14 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr
offset, unsigned size)
r = s->cfg1;
break;
case A_CFG2:
- if (scc_partno(s) != 0x524) {
+ if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
/* CFG2 reserved on other boards */
goto bad_offset;
}
r = s->cfg2;
break;
case A_CFG3:
- if (scc_partno(s) == 0x524) {
+ if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) {
/* CFG3 reserved on AN524 */
goto bad_offset;
}
@@ -130,7 +130,7 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset,
unsigned size)
r = s->cfg4;
break;
case A_CFG5:
- if (scc_partno(s) != 0x524) {
+ if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
/* CFG5 reserved on other boards */
goto bad_offset;
}
@@ -185,7 +185,10 @@ static void mps2_scc_write(void *opaque, hwaddr offset,
uint64_t value,
switch (offset) {
case A_CFG0:
- /* TODO on some boards bit 0 controls RAM remapping */
+ /*
+ * TODO on some boards bit 0 controls RAM remapping;
+ * on others bit 1 is CPU_WAIT.
+ */
s->cfg0 = value;
break;
case A_CFG1:
@@ -195,7 +198,7 @@ static void mps2_scc_write(void *opaque, hwaddr offset,
uint64_t value,
}
break;
case A_CFG2:
- if (scc_partno(s) != 0x524) {
+ if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
/* CFG2 reserved on other boards */
goto bad_offset;
}
@@ -203,7 +206,7 @@ static void mps2_scc_write(void *opaque, hwaddr offset,
uint64_t value,
s->cfg2 = value;
break;
case A_CFG5:
- if (scc_partno(s) != 0x524) {
+ if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
/* CFG5 reserved on other boards */
goto bad_offset;
}
--
2.20.1
- [PULL 30/54] hw/arm/armsse: Add missing SSE-200 SYS_PPU, (continued)
- [PULL 30/54] hw/arm/armsse: Add missing SSE-200 SYS_PPU, Peter Maydell, 2021/03/08
- [PULL 22/54] hw/arm/armsse: Add a define for number of IRQs used by the SSE itself, Peter Maydell, 2021/03/08
- [PULL 32/54] hw/arm/armsse: Add support for SSE variants with a system counter, Peter Maydell, 2021/03/08
- [PULL 19/54] hw/arm/Kconfig: Move ARMSSE_CPUID and ARMSSE_MHU stanzas to hw/misc, Peter Maydell, 2021/03/08
- [PULL 18/54] hw/misc/iotkit-sysctl: Implement SSE-200 and SSE-300 PID register values, Peter Maydell, 2021/03/08
- [PULL 27/54] hw/arm/armsse: Move sysinfo register block into data-driven framework, Peter Maydell, 2021/03/08
- [PULL 28/54] hw/arm/armsse: Move sysctl register block into data-driven framework, Peter Maydell, 2021/03/08
- [PULL 31/54] hw/arm/armsse: Indirect irq_is_common[] through ARMSSEInfo, Peter Maydell, 2021/03/08
- [PULL 29/54] hw/arm/armsse: Move PPUs into data-driven framework, Peter Maydell, 2021/03/08
- [PULL 38/54] hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register, Peter Maydell, 2021/03/08
- [PULL 39/54] hw/misc/mps2-scc: Implement changes for AN547,
Peter Maydell <=
- [PULL 24/54] hw/arm/armsse: Move dual-timer device into data-driven framework, Peter Maydell, 2021/03/08
- [PULL 33/54] hw/arm/armsse: Add support for TYPE_SSE_TIMER in ARMSSEDeviceInfo, Peter Maydell, 2021/03/08
- [PULL 34/54] hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL block, Peter Maydell, 2021/03/08
- [PULL 44/54] tests/qtest/sse-timer-test: Add simple test of the SSE counter, Peter Maydell, 2021/03/08
- [PULL 36/54] hw/arm/mps2-tz: Make UART overflow IRQ board-specific, Peter Maydell, 2021/03/08
- [PULL 35/54] hw/arm/armsse: Add SSE-300 support, Peter Maydell, 2021/03/08
- [PULL 40/54] hw/arm/mps2-tz: Support running APB peripherals on different clock, Peter Maydell, 2021/03/08
- [PULL 42/54] hw/arm/mps2-tz: Add new mps3-an547 board, Peter Maydell, 2021/03/08
- [PULL 43/54] docs/system/arm/mps2.rst: Document the new mps3-an547 board, Peter Maydell, 2021/03/08
- [PULL 41/54] hw/arm/mps2-tz: Make initsvtor0 setting board-specific, Peter Maydell, 2021/03/08