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[RFC PATCH v2 02/22] target/mips/tx79: Move MTHI1 / MTLO1 opcodes to dec
From: |
Philippe Mathieu-Daudé |
Subject: |
[RFC PATCH v2 02/22] target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree |
Date: |
Tue, 9 Mar 2021 15:56:33 +0100 |
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-10-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tx79.decode | 3 +++
target/mips/translate.c | 25 -------------------------
target/mips/tx79_translate.c | 14 ++++++++++++++
3 files changed, 17 insertions(+), 25 deletions(-)
diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index 2e287ebbf36..30737da54e4 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -17,9 +17,12 @@
# Named instruction formats. These are generally used to
# reduce the amount of duplication between instruction patterns.
+@rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0
@rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0
###########################################################################
MFHI1 011100 0000000000 ..... 00000 010000 @rd
+MTHI1 011100 ..... 0000000000 00000 010001 @rs
MFLO1 011100 0000000000 ..... 00000 010010 @rd
+MTLO1 011100 ..... 0000000000 00000 010011 @rs
diff --git a/target/mips/translate.c b/target/mips/translate.c
index aa35d0f680e..0131affce70 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1360,8 +1360,6 @@ enum {
MMI_OPC_PLZCW = 0x04 | MMI_OPC_CLASS_MMI,
MMI_OPC_CLASS_MMI0 = 0x08 | MMI_OPC_CLASS_MMI,
MMI_OPC_CLASS_MMI2 = 0x09 | MMI_OPC_CLASS_MMI,
- MMI_OPC_MTHI1 = 0x11 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MTHI */
- MMI_OPC_MTLO1 = 0x13 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MTLO */
MMI_OPC_MULT1 = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */
MMI_OPC_MULTU1 = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */
MMI_OPC_DIV1 = 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIV */
@@ -3462,25 +3460,6 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
tcg_temp_free(t1);
}
-#if defined(TARGET_MIPS64)
-/* Copy GPR to and from TX79 HI1/LO1 register. */
-static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
-{
- switch (opc) {
- case MMI_OPC_MTHI1:
- gen_load_gpr(cpu_HI[1], reg);
- break;
- case MMI_OPC_MTLO1:
- gen_load_gpr(cpu_LO[1], reg);
- break;
- default:
- MIPS_INVAL("mfthilo1 TX79");
- gen_reserved_instruction(ctx);
- break;
- }
-}
-#endif
-
/* Arithmetic on HI/LO registers */
static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
{
@@ -25108,10 +25087,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext
*ctx)
case MMI_OPC_DIVU1:
gen_div1_tx79(ctx, opc, rs, rt);
break;
- case MMI_OPC_MTLO1:
- case MMI_OPC_MTHI1:
- gen_HILO1_tx79(ctx, opc, rs);
- break;
case MMI_OPC_PLZCW: /* TODO: MMI_OPC_PLZCW */
case MMI_OPC_PMFHL: /* TODO: MMI_OPC_PMFHL */
case MMI_OPC_PMTHL: /* TODO: MMI_OPC_PMTHL */
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 22bd6033e55..905245cece7 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -35,3 +35,17 @@ static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a)
return true;
}
+
+static bool trans_MTHI1(DisasContext *ctx, arg_rtype *a)
+{
+ gen_load_gpr(cpu_HI[1], a->rs);
+
+ return true;
+}
+
+static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
+{
+ gen_load_gpr(cpu_LO[1], a->rs);
+
+ return true;
+}
--
2.26.2
- [RFC PATCH v2 00/22] target/mips: Reintroduce the R5900 CPU (without testing), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 01/22] target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 02/22] target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree,
Philippe Mathieu-Daudé <=
- [RFC PATCH v2 03/22] target/mips/translate: Make gen_rdhwr() public, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 04/22] target/mips/translate: Simplify PCPYH using deposit_i64(), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 05/22] target/mips/tx79: Move PCPYH opcode to decodetree, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 06/22] target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 07/22] target/mips: Remove 'C790 Multimedia Instructions' dead code, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 08/22] target/mips/tx79: Salvage instructions description comment, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 09/22] target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 10/22] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 11/22] target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word), Philippe Mathieu-Daudé, 2021/03/09