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[RFC PATCH v2 04/22] target/mips/translate: Simplify PCPYH using deposit
From: |
Philippe Mathieu-Daudé |
Subject: |
[RFC PATCH v2 04/22] target/mips/translate: Simplify PCPYH using deposit_i64() |
Date: |
Tue, 9 Mar 2021 15:56:35 +0100 |
Simplify the PCPYH (Parallel Copy Halfword) instruction by using
multiple calls to deposit_i64() which can be optimized by some
TCG backends.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-11-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 34 ++++------------------------------
1 file changed, 4 insertions(+), 30 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0f77c0ebc57..9de81b08665 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24091,36 +24091,10 @@ static void gen_mmi_pcpyh(DisasContext *ctx)
tcg_gen_movi_i64(cpu_gpr[rd], 0);
tcg_gen_movi_i64(cpu_gpr_hi[rd], 0);
} else {
- TCGv_i64 t0 = tcg_temp_new();
- TCGv_i64 t1 = tcg_temp_new();
- uint64_t mask = (1ULL << 16) - 1;
-
- tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
- tcg_gen_movi_i64(t1, 0);
- tcg_gen_or_i64(t1, t0, t1);
- tcg_gen_shli_i64(t0, t0, 16);
- tcg_gen_or_i64(t1, t0, t1);
- tcg_gen_shli_i64(t0, t0, 16);
- tcg_gen_or_i64(t1, t0, t1);
- tcg_gen_shli_i64(t0, t0, 16);
- tcg_gen_or_i64(t1, t0, t1);
-
- tcg_gen_mov_i64(cpu_gpr[rd], t1);
-
- tcg_gen_andi_i64(t0, cpu_gpr_hi[rt], mask);
- tcg_gen_movi_i64(t1, 0);
- tcg_gen_or_i64(t1, t0, t1);
- tcg_gen_shli_i64(t0, t0, 16);
- tcg_gen_or_i64(t1, t0, t1);
- tcg_gen_shli_i64(t0, t0, 16);
- tcg_gen_or_i64(t1, t0, t1);
- tcg_gen_shli_i64(t0, t0, 16);
- tcg_gen_or_i64(t1, t0, t1);
-
- tcg_gen_mov_i64(cpu_gpr_hi[rd], t1);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
+ tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rt], cpu_gpr[rt], 16, 16);
+ tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rd], cpu_gpr[rd], 32, 32);
+ tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt], cpu_gpr_hi[rt],
16, 16);
+ tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rd], cpu_gpr_hi[rd],
32, 32);
}
}
--
2.26.2
- [RFC PATCH v2 00/22] target/mips: Reintroduce the R5900 CPU (without testing), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 01/22] target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 02/22] target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 03/22] target/mips/translate: Make gen_rdhwr() public, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 04/22] target/mips/translate: Simplify PCPYH using deposit_i64(),
Philippe Mathieu-Daudé <=
- [RFC PATCH v2 05/22] target/mips/tx79: Move PCPYH opcode to decodetree, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 06/22] target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 07/22] target/mips: Remove 'C790 Multimedia Instructions' dead code, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 08/22] target/mips/tx79: Salvage instructions description comment, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 09/22] target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 10/22] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 11/22] target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 12/22] target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower), Philippe Mathieu-Daudé, 2021/03/09