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[PATCH 1/8] target/mips: Remove unused register from MSA 2R/2RF instruct
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 1/8] target/mips: Remove unused register from MSA 2R/2RF instruction format |
Date: |
Sun, 3 Oct 2021 19:57:36 +0200 |
Commits cbe50b9a8e7 ("target-mips: add MSA VEC/2R format instructions")
and 3bdeb68866e ("target-mips: add MSA 2RF format instructions") added
the MSA 2R/2RF instructions. However these instructions don't use any
target vector register, so remove the unused TCG temporaries.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: Reworded, removing the Fixes: tag.
---
target/mips/tcg/msa_translate.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 8170a8df26b..ee6424126f7 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -1942,13 +1942,11 @@ static void gen_msa_2r(DisasContext *ctx)
{
#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
(op & (0x7 << 18)))
- uint8_t wt = (ctx->opcode >> 16) & 0x1f;
uint8_t ws = (ctx->opcode >> 11) & 0x1f;
uint8_t wd = (ctx->opcode >> 6) & 0x1f;
uint8_t df = (ctx->opcode >> 16) & 0x3;
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 twt = tcg_const_i32(wt);
TCGv_i32 tdf = tcg_const_i32(df);
switch (MASK_MSA_2R(ctx->opcode)) {
@@ -2018,7 +2016,6 @@ static void gen_msa_2r(DisasContext *ctx)
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
- tcg_temp_free_i32(twt);
tcg_temp_free_i32(tdf);
}
@@ -2026,13 +2023,11 @@ static void gen_msa_2rf(DisasContext *ctx)
{
#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
(op & (0xf << 17)))
- uint8_t wt = (ctx->opcode >> 16) & 0x1f;
uint8_t ws = (ctx->opcode >> 11) & 0x1f;
uint8_t wd = (ctx->opcode >> 6) & 0x1f;
uint8_t df = (ctx->opcode >> 16) & 0x1;
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 twt = tcg_const_i32(wt);
/* adjust df value for floating-point instruction */
TCGv_i32 tdf = tcg_const_i32(df + 2);
@@ -2089,7 +2084,6 @@ static void gen_msa_2rf(DisasContext *ctx)
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
- tcg_temp_free_i32(twt);
tcg_temp_free_i32(tdf);
}
--
2.31.1
- [PATCH 0/8] target/mips: Use tcg_constant_*, Philippe Mathieu-Daudé, 2021/10/03
- [PATCH 1/8] target/mips: Remove unused register from MSA 2R/2RF instruction format,
Philippe Mathieu-Daudé <=
- [PATCH 2/8] target/mips: Use tcg_constant_i32() in gen_msa_elm_df(), Philippe Mathieu-Daudé, 2021/10/03
- [PATCH 3/8] target/mips: Use tcg_constant_i32() in gen_msa_2rf(), Philippe Mathieu-Daudé, 2021/10/03
- [PATCH 4/8] target/mips: Use tcg_constant_i32() in gen_msa_2r(), Philippe Mathieu-Daudé, 2021/10/03
- [PATCH 5/8] target/mips: Use tcg_constant_i32() in gen_msa_3rf(), Philippe Mathieu-Daudé, 2021/10/03
- [PATCH 6/8] target/mips: Use explicit extract32() calls in gen_msa_i5(), Philippe Mathieu-Daudé, 2021/10/03