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[PULL 02/26] target/riscv: fix clzw implementation to operate on arg1
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From: |
Alistair Francis |
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Subject: |
[PULL 02/26] target/riscv: fix clzw implementation to operate on arg1 |
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Date: |
Thu, 7 Oct 2021 16:47:27 +1000 |
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
The refactored gen_clzw() uses ret as its argument, instead of arg1.
Fix it.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210911140016.834071-3-philipp.tomsich@vrull.eu
Fixes: 60903915050 ("target/riscv: Add DisasExtend to gen_unary")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvb.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index c0a6e25826..6c85c89f6d 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -349,7 +349,7 @@ GEN_TRANS_SHADD(3)
static void gen_clzw(TCGv ret, TCGv arg1)
{
- tcg_gen_clzi_tl(ret, ret, 64);
+ tcg_gen_clzi_tl(ret, arg1, 64);
tcg_gen_subi_tl(ret, ret, 32);
}
--
2.31.1
- [PULL 00/26] riscv-to-apply queue, Alistair Francis, 2021/10/07
- [PULL 01/26] target/riscv: Introduce temporary in gen_add_uw(), Alistair Francis, 2021/10/07
- [PULL 02/26] target/riscv: fix clzw implementation to operate on arg1,
Alistair Francis <=
- [PULL 03/26] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Alistair Francis, 2021/10/07
- [PULL 04/26] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Alistair Francis, 2021/10/07
- [PULL 05/26] target/riscv: Reassign instructions to the Zba-extension, Alistair Francis, 2021/10/07
- [PULL 06/26] target/riscv: Remove the W-form instructions from Zbs, Alistair Francis, 2021/10/07
- [PULL 07/26] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B), Alistair Francis, 2021/10/07
- [PULL 08/26] target/riscv: Reassign instructions to the Zbs-extension, Alistair Francis, 2021/10/07
- [PULL 09/26] target/riscv: Add instructions of the Zbc-extension, Alistair Francis, 2021/10/07
- [PULL 10/26] target/riscv: Reassign instructions to the Zbb-extension, Alistair Francis, 2021/10/07
- [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Alistair Francis, 2021/10/07