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[PULL 03/26] target/riscv: clwz must ignore high bits (use shift-left &
From: |
Alistair Francis |
Subject: |
[PULL 03/26] target/riscv: clwz must ignore high bits (use shift-left & changed logic) |
Date: |
Thu, 7 Oct 2021 16:47:28 +1000 |
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
Assume clzw being executed on a register that is not sign-extended, such
as for the following sequence that uses (1ULL << 63) | 392 as the operand
to clzw:
bseti a2, zero, 63
addi a2, a2, 392
clzw a3, a2
The correct result of clzw would be 23, but the current implementation
returns -32 (as it performs a 64bit clz, which results in 0 leading zero
bits, and then subtracts 32).
Fix this by changing the implementation to:
1. shift the original register up by 32
2. performs a target-length (64bit) clz
3. return 32 if no bits are set
Marking this instruction as 'w-form' (i.e., setting ctx->w) would not
correctly model the behaviour, as the instruction should not perform
a zero-extensions on the input (after all, it is not a .uw instruction)
and the result is always in the range 0..32 (so neither a sign-extension
nor a zero-extension on the result will ever be needed). Consequently,
we do not set ctx->w and mark the instruction as EXT_NONE.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
Message-id: 20210911140016.834071-4-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvb.c.inc | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 6c85c89f6d..73d1e45026 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -349,15 +349,17 @@ GEN_TRANS_SHADD(3)
static void gen_clzw(TCGv ret, TCGv arg1)
{
- tcg_gen_clzi_tl(ret, arg1, 64);
- tcg_gen_subi_tl(ret, ret, 32);
+ TCGv t = tcg_temp_new();
+ tcg_gen_shli_tl(t, arg1, 32);
+ tcg_gen_clzi_tl(ret, t, 32);
+ tcg_temp_free(t);
}
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
- return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
+ return gen_unary(ctx, a, EXT_NONE, gen_clzw);
}
static void gen_ctzw(TCGv ret, TCGv arg1)
--
2.31.1
- [PULL 00/26] riscv-to-apply queue, Alistair Francis, 2021/10/07
- [PULL 01/26] target/riscv: Introduce temporary in gen_add_uw(), Alistair Francis, 2021/10/07
- [PULL 02/26] target/riscv: fix clzw implementation to operate on arg1, Alistair Francis, 2021/10/07
- [PULL 03/26] target/riscv: clwz must ignore high bits (use shift-left & changed logic),
Alistair Francis <=
- [PULL 04/26] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Alistair Francis, 2021/10/07
- [PULL 05/26] target/riscv: Reassign instructions to the Zba-extension, Alistair Francis, 2021/10/07
- [PULL 06/26] target/riscv: Remove the W-form instructions from Zbs, Alistair Francis, 2021/10/07
- [PULL 07/26] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B), Alistair Francis, 2021/10/07
- [PULL 08/26] target/riscv: Reassign instructions to the Zbs-extension, Alistair Francis, 2021/10/07
- [PULL 09/26] target/riscv: Add instructions of the Zbc-extension, Alistair Francis, 2021/10/07
- [PULL 10/26] target/riscv: Reassign instructions to the Zbb-extension, Alistair Francis, 2021/10/07
- [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Alistair Francis, 2021/10/07