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Re: [PATCH 2/8] accel/tcg: Split out g2h_tlbe
From: |
Alistair Francis |
Subject: |
Re: [PATCH 2/8] accel/tcg: Split out g2h_tlbe |
Date: |
Tue, 12 Oct 2021 09:19:33 +1000 |
On Mon, Oct 11, 2021 at 3:44 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Create a new function to combine a CPUTLBEntry addend
> with the guest address to form a host address.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> accel/tcg/cputlb.c | 24 ++++++++++++++----------
> 1 file changed, 14 insertions(+), 10 deletions(-)
>
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index 46140ccff3..761f726722 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -90,6 +90,11 @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast)
> return fast->mask + (1 << CPU_TLB_ENTRY_BITS);
> }
>
> +static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gaddr)
> +{
> + return tlb->addend + (uintptr_t)gaddr;
> +}
> +
> static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
> size_t max_entries)
> {
> @@ -976,8 +981,7 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry
> *tlb_entry,
>
> if ((addr & (TLB_INVALID_MASK | TLB_MMIO |
> TLB_DISCARD_WRITE | TLB_NOTDIRTY)) == 0) {
> - addr &= TARGET_PAGE_MASK;
> - addr += tlb_entry->addend;
> + addr = g2h_tlbe(tlb_entry, addr & TARGET_PAGE_MASK);
> if ((addr - start) < length) {
> #if TCG_OVERSIZED_GUEST
> tlb_entry->addr_write |= TLB_NOTDIRTY;
> @@ -1527,7 +1531,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState
> *env, target_ulong addr,
> return -1;
> }
>
> - p = (void *)((uintptr_t)addr + entry->addend);
> + p = (void *)g2h_tlbe(entry, addr);
> if (hostp) {
> *hostp = p;
> }
> @@ -1619,7 +1623,7 @@ static int probe_access_internal(CPUArchState *env,
> target_ulong addr,
> }
>
> /* Everything else is RAM. */
> - *phost = (void *)((uintptr_t)addr + entry->addend);
> + *phost = (void *)g2h_tlbe(entry, addr);
> return flags;
> }
>
> @@ -1727,7 +1731,7 @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong
> addr, int mmu_idx,
> data->v.io.offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
> } else {
> data->is_io = false;
> - data->v.ram.hostaddr = (void *)((uintptr_t)addr + tlbe->addend);
> + data->v.ram.hostaddr = (void *)g2h_tlbe(tlbe, addr);
> }
> return true;
> } else {
> @@ -1826,7 +1830,7 @@ static void *atomic_mmu_lookup(CPUArchState *env,
> target_ulong addr,
> goto stop_the_world;
> }
>
> - hostaddr = (void *)((uintptr_t)addr + tlbe->addend);
> + hostaddr = (void *)g2h_tlbe(tlbe, addr);
>
> if (unlikely(tlb_addr & TLB_NOTDIRTY)) {
> notdirty_write(env_cpu(env), addr, size,
> @@ -1938,7 +1942,7 @@ load_helper(CPUArchState *env, target_ulong addr,
> MemOpIdx oi,
> access_type, op ^ (need_swap * MO_BSWAP));
> }
>
> - haddr = (void *)((uintptr_t)addr + entry->addend);
> + haddr = (void *)g2h_tlbe(entry, addr);
>
> /*
> * Keep these two load_memop separate to ensure that the compiler
> @@ -1975,7 +1979,7 @@ load_helper(CPUArchState *env, target_ulong addr,
> MemOpIdx oi,
> return res & MAKE_64BIT_MASK(0, size * 8);
> }
>
> - haddr = (void *)((uintptr_t)addr + entry->addend);
> + haddr = (void *)g2h_tlbe(entry, addr);
> return load_memop(haddr, op);
> }
>
> @@ -2467,7 +2471,7 @@ store_helper(CPUArchState *env, target_ulong addr,
> uint64_t val,
> notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr);
> }
>
> - haddr = (void *)((uintptr_t)addr + entry->addend);
> + haddr = (void *)g2h_tlbe(entry, addr);
>
> /*
> * Keep these two store_memop separate to ensure that the compiler
> @@ -2492,7 +2496,7 @@ store_helper(CPUArchState *env, target_ulong addr,
> uint64_t val,
> return;
> }
>
> - haddr = (void *)((uintptr_t)addr + entry->addend);
> + haddr = (void *)g2h_tlbe(entry, addr);
> store_memop(haddr, val, op);
> }
>
> --
> 2.25.1
>
>
- [PATCH 5/8] linux-user: Support TCG_TARGET_SIGNED_ADDR32, (continued)
- [PATCH 5/8] linux-user: Support TCG_TARGET_SIGNED_ADDR32, Richard Henderson, 2021/10/10
- [PATCH 4/8] accel/tcg: Add guest_base_signed_addr32 for user-only, Richard Henderson, 2021/10/10
- [PATCH 2/8] accel/tcg: Split out g2h_tlbe, Richard Henderson, 2021/10/10
- [PATCH 8/8] target/riscv: Support TCG_TARGET_SIGNED_ADDR32, Richard Henderson, 2021/10/10
- [PATCH 6/8] tcg/aarch64: Support TCG_TARGET_SIGNED_ADDR32, Richard Henderson, 2021/10/10
- [PATCH 7/8] target/mips: Support TCG_TARGET_SIGNED_ADDR32, Richard Henderson, 2021/10/10