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[PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
From: |
frank . chang |
Subject: |
[PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits |
Date: |
Fri, 15 Oct 2021 15:46:13 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
--
---
target/riscv/cpu.h | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9b2af4e4d0e..49eece111e2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -101,7 +101,7 @@ typedef struct CPURISCVState CPURISCVState;
#include "pmp.h"
#endif
-#define RV_VLEN_MAX 256
+#define RV_VLEN_MAX 1024
FIELD(VTYPE, VLMUL, 0, 3)
FIELD(VTYPE, VSEW, 3, 3)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 92a23b52e49..dcb96c954ec 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -567,8 +567,8 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1,
uint32_t data,
base = get_gpr(s, rs1, EXT_NONE);
/*
- * As simd_desc supports at most 256 bytes, and in this implementation,
- * the max vector group length is 2048 bytes. So split it into two parts.
+ * As simd_desc supports at most 2048 bytes, and in this implementation,
+ * the max vector group length is 4096 bytes. So split it into two parts.
*
* The first part is vlen in bytes, encoded in maxsz of simd_desc.
* The second part is lmul, encoded in data of simd_desc.
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 37b2451bd05..70ddc55e16b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -124,7 +124,7 @@ static inline int32_t vext_lmul(uint32_t desc)
static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
{
/*
- * As simd_desc support at most 256 bytes, the max vlen is 256 bits.
+ * As simd_desc support at most 2048 bytes, the max vlen is 1024 bits.
* so vlen in bytes (vlenb) is encoded as maxsz.
*/
uint32_t vlenb = simd_maxsz(desc);
--
2.25.1
- [PATCH v8 59/78] target/riscv: rvv-1.0: floating-point min/max instructions, (continued)
- [PATCH v8 59/78] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 2021/10/15
- [PATCH v8 60/78] target/riscv: introduce floating-point rounding mode enum, frank . chang, 2021/10/15
- [PATCH v8 61/78] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2021/10/15
- [PATCH v8 62/78] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2021/10/15
- [PATCH v8 63/78] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2021/10/15
- [PATCH v8 64/78] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2021/10/15
- [PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits,
frank . chang <=
- [PATCH v8 66/78] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/10/15
- [PATCH v8 67/78] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/10/15
- [PATCH v8 68/78] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs, frank . chang, 2021/10/15
- [PATCH v8 69/78] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/10/15
- [PATCH v8 70/78] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/10/15
- [PATCH v8 71/78] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, frank . chang, 2021/10/15
- [PATCH v8 72/78] target/riscv: set mstatus.SD bit when writing fp CSRs, frank . chang, 2021/10/15
- [PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, frank . chang, 2021/10/15