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Re: [PATCH v8 62/78] target/riscv: rvv-1.0: widening floating-point/inte


From: Alistair Francis
Subject: Re: [PATCH v8 62/78] target/riscv: rvv-1.0: widening floating-point/integer type-convert
Date: Tue, 26 Oct 2021 16:29:25 +1000

On Fri, Oct 15, 2021 at 6:47 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Add the following instructions:
>
> * vfwcvt.rtz.xu.f.v
> * vfwcvt.rtz.x.f.v
>
> Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point
> rounding modes.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/helper.h                   |  2 +
>  target/riscv/insn32.decode              | 13 +++---
>  target/riscv/insn_trans/trans_rvv.c.inc | 55 +++++++++++++++++++++----
>  target/riscv/vector_helper.c            |  7 +++-
>  4 files changed, 63 insertions(+), 14 deletions(-)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 1727075dce4..53cf88cd402 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -928,8 +928,10 @@ DEF_HELPER_5(vfwcvt_xu_f_v_h, void, ptr, ptr, ptr, env, 
> i32)
>  DEF_HELPER_5(vfwcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_5(vfwcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_5(vfwcvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfwcvt_f_xu_v_b, void, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_5(vfwcvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_5(vfwcvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfwcvt_f_x_v_b, void, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_5(vfwcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 02064f8ec98..664d0fb3716 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -592,11 +592,14 @@ vfcvt_f_xu_v       010010 . ..... 00010 001 ..... 
> 1010111 @r2_vm
>  vfcvt_f_x_v        010010 . ..... 00011 001 ..... 1010111 @r2_vm
>  vfcvt_rtz_xu_f_v   010010 . ..... 00110 001 ..... 1010111 @r2_vm
>  vfcvt_rtz_x_f_v    010010 . ..... 00111 001 ..... 1010111 @r2_vm
> -vfwcvt_xu_f_v   100010 . ..... 01000 001 ..... 1010111 @r2_vm
> -vfwcvt_x_f_v    100010 . ..... 01001 001 ..... 1010111 @r2_vm
> -vfwcvt_f_xu_v   100010 . ..... 01010 001 ..... 1010111 @r2_vm
> -vfwcvt_f_x_v    100010 . ..... 01011 001 ..... 1010111 @r2_vm
> -vfwcvt_f_f_v    100010 . ..... 01100 001 ..... 1010111 @r2_vm
> +
> +vfwcvt_xu_f_v      010010 . ..... 01000 001 ..... 1010111 @r2_vm
> +vfwcvt_x_f_v       010010 . ..... 01001 001 ..... 1010111 @r2_vm
> +vfwcvt_f_xu_v      010010 . ..... 01010 001 ..... 1010111 @r2_vm
> +vfwcvt_f_x_v       010010 . ..... 01011 001 ..... 1010111 @r2_vm
> +vfwcvt_f_f_v       010010 . ..... 01100 001 ..... 1010111 @r2_vm
> +vfwcvt_rtz_xu_f_v  010010 . ..... 01110 001 ..... 1010111 @r2_vm
> +vfwcvt_rtz_x_f_v   010010 . ..... 01111 001 ..... 1010111 @r2_vm
>  vfncvt_xu_f_v   100010 . ..... 10000 001 ..... 1010111 @r2_vm
>  vfncvt_x_f_v    100010 . ..... 10001 001 ..... 1010111 @r2_vm
>  vfncvt_f_xu_v   100010 . ..... 10010 001 ..... 1010111 @r2_vm
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index b1ea15517c0..63d33b22068 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2535,12 +2535,55 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr 
> *a)
>             vext_check_ds(s, a->rd, a->rs2, a->vm);
>  }
>
> -#define GEN_OPFV_WIDEN_TRANS(NAME)                                 \
> +#define GEN_OPFV_WIDEN_TRANS(NAME, HELPER, FRM)                    \
>  static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
>  {                                                                  \
>      if (opfv_widen_check(s, a)) {                                  \
>          uint32_t data = 0;                                         \
>          static gen_helper_gvec_3_ptr * const fns[2] = {            \
> +            gen_helper_##HELPER##_h,                               \
> +            gen_helper_##HELPER##_w,                               \
> +        };                                                         \
> +        TCGLabel *over = gen_new_label();                          \
> +        gen_set_rm(s, FRM);                                        \
> +        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
> +                                                                   \
> +        data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
> +        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
> +        tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
> +                           vreg_ofs(s, a->rs2), cpu_env,           \
> +                           s->vlen / 8, s->vlen / 8, data,         \
> +                           fns[s->sew - 1]);                       \
> +        mark_vs_dirty(s);                                          \
> +        gen_set_label(over);                                       \
> +        return true;                                               \
> +    }                                                              \
> +    return false;                                                  \
> +}
> +
> +GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v, vfwcvt_xu_f_v, RISCV_FRM_DYN)
> +GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v, vfwcvt_x_f_v, RISCV_FRM_DYN)
> +GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v, vfwcvt_f_f_v, RISCV_FRM_DYN)
> +/* Reuse the helper functions from vfwcvt.xu.f.v and vfwcvt.x.f.v */
> +GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_xu_f_v, vfwcvt_xu_f_v, RISCV_FRM_RTZ)
> +GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_x_f_v, vfwcvt_x_f_v, RISCV_FRM_RTZ)
> +
> +static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
> +{
> +    return require_rvv(s) &&
> +           require_scale_rvf(s) &&
> +           vext_check_isa_ill(s) &&
> +           /* OPFV widening instructions ignore vs1 check */
> +           vext_check_ds(s, a->rd, a->rs2, a->vm);
> +}
> +
> +#define GEN_OPFXV_WIDEN_TRANS(NAME)                                \
> +static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
> +{                                                                  \
> +    if (opfxv_widen_check(s, a)) {                                 \
> +        uint32_t data = 0;                                         \
> +        static gen_helper_gvec_3_ptr * const fns[3] = {            \
> +            gen_helper_##NAME##_b,                                 \
>              gen_helper_##NAME##_h,                                 \
>              gen_helper_##NAME##_w,                                 \
>          };                                                         \
> @@ -2549,11 +2592,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) 
>              \
>          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
>                                                                     \
>          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
> -        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
>          tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
>                             vreg_ofs(s, a->rs2), cpu_env,           \
>                             s->vlen / 8, s->vlen / 8, data,         \
> -                           fns[s->sew - 1]);                       \
> +                           fns[s->sew]);                           \
>          mark_vs_dirty(s);                                          \
>          gen_set_label(over);                                       \
>          return true;                                               \
> @@ -2561,11 +2603,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)  
>             \
>      return false;                                                  \
>  }
>
> -GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v)
> -GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v)
> -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v)
> -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v)
> -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v)
> +GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_xu_v)
> +GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_x_v)
>
>  /* Narrowing Floating-Point/Integer Type-Convert Instructions */
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index c19cd937e1a..dda8e2ab5a2 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -3773,6 +3773,7 @@ GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8)
>
>  /* Widening Floating-Point/Integer Type-Convert Instructions */
>  /* (TD, T2, TX2) */
> +#define WOP_UU_B uint16_t, uint8_t,  uint8_t
>  #define WOP_UU_H uint32_t, uint16_t, uint16_t
>  #define WOP_UU_W uint64_t, uint32_t, uint32_t
>  /* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned 
> integer.*/
> @@ -3788,19 +3789,23 @@ GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 2, 4)
>  GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 4, 8)
>
>  /* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width 
> float */
> +RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16)
>  RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32)
>  RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64)
> +GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b, 1, 2)
>  GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 2, 4)
>  GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 4, 8)
>
>  /* vfwcvt.f.x.v vd, vs2, vm # Convert integer to double-width float. */
> +RVVCALL(OPFVV1, vfwcvt_f_x_v_b, WOP_UU_B, H2, H1, int8_to_float16)
>  RVVCALL(OPFVV1, vfwcvt_f_x_v_h, WOP_UU_H, H4, H2, int16_to_float32)
>  RVVCALL(OPFVV1, vfwcvt_f_x_v_w, WOP_UU_W, H8, H4, int32_to_float64)
> +GEN_VEXT_V_ENV(vfwcvt_f_x_v_b, 1, 2)
>  GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 2, 4)
>  GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 4, 8)
>
>  /*
> - * vfwcvt.f.f.v vd, vs2, vm #
> + * vfwcvt.f.f.v vd, vs2, vm
>   * Convert single-width float to double-width float.
>   */
>  static uint32_t vfwcvtffv16(uint16_t a, float_status *s)
> --
> 2.25.1
>
>



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